Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 305
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
Table 22. Write Register 4 Rx and Tx Control
Parity (D0)
If this bit is set, an additional bit position is added to transmitted data and is
expected in receive data. This added bit position is in addition to those bits
specified in the bits/character control. In the Receive mode, the parity bit
received is transferred to the CPU as part of the character, unless eight bits/
character is selected.
Parity Even/Odd (D1)
If parity is specified, this bit determines whether the bit is sent and checked
as even or odd (1 = even).
Stop Bits 0 and 1 (D2 and D3)
These bits determine the number of stop bits added to each asynchronous
character sent. The receiver always checks for one stop bit. A special mode
(00) designates that a synchronous mode is to be selected.
Table 23. Stop Bits
D3
Stop Bits 1
0
0
1
1
Rate 1
Clock
D7
Rate 0
Clock
D6
D2
Stop Bits 0
0
1
0
1
Modes 1
Sync
D5
Modes 0
Sync
D4
Result
Sync modes
1 stop bit per character
1-1/2 stop bits per character
2 stop bits per character
Bits 1
Stop
D3
Bits 0
Z80 CPU Peripherals
Stop
D2
Serial Input/Output
Parity
Even/
User Manual
Odd
D1
Parity
D0
285
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