IDT79R3041-20J IDT, Integrated Device Technology Inc, IDT79R3041-20J Datasheet - Page 12

• Manufacturer Part Number: IDT79R3041-20J
• Description: IC MPU 32BIT 5V 20MHZ 84-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R3041-20J

• Processor Type: RISC 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R3041-20J

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
PIN DESCRIPTION (Continued):
PIN NAME
Burst/
WrNear
Rd
Wr
Ack
RdCEn
SysClk
BusReq
BusGnt
SBrCond(3)/
IOStrobe
SBrCond(2)/
ExtDataEn
MemStrobe
O
O
O
I
I
O
I
O
I/O
I/O
O
I/O
Burst Transfer/Write Near: On read transactions, the
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles
if the 4-word data block refill option is selected in the CP0 Cache Config Register.
On write transactions, the
is performing back-to-back write transactions to an address within the same 256 byte page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows nearby writes to be retired quickly.
Read: An output which indicates that the current bus transaction is a read.
Write: An output which indicates that the current bus transaction is a write.
Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction. On write transactions, this signal indicates that the CPU may either
progress to the next data item (for mini-burst writes of wide datums to narrow memories), or terminate
the write cycle. On read transactions, this signal indicates that the memory system has sufficiently
processed the read, and that the processor core may begin processing the data from this read transfer.
Read Buffer Clock Enable: An input which indicates to the device that the memory system has
placed valid data on the A/D bus, and that the processor may move the data into the on-chip Read
Buffer.
System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "System" clock. This clock is used to control state transitions in the read buffer, write buffer,
memory controller, and bus interface unit.
DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus
interface signals so that they may be driven by an external master. The negation of this input relinquishes
mastership back to the CPU.
DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a
detected, and that the bus is relinquished to the external master.
The R3041 adds an additional DMA protocol, under the control of CP0. If the DMA Protocol is enabled,
the R3041 can request that the external master relinquish bus mastership back to the processor by
negating the
Branch Condition Port/IO Strobe: The use of this signal depends on the setting of various bits of the
CP0 Bus Control register. If BrCond mode is selected, this input is logically connected to CpCond(3),
and can be used by the branch on co-processor condition instructions as an input port. The SBrCond(3)
input has special internal logic to synchronize the input, and thus may be driven by asynchronous
agents.
If this pin is selected to function as
as programmed into CP0. This strobe asserts in the second clock cycle of a transfer, and thus can be
used to strobe various control signals on the bus interface.
Branch Condition Port/Extended Data Enable: The use of this signal depends on the settings in the
CP0 Bus Control register. If BrCond mode is selected, this input is logically connected to CpCond(2),
and can be used by the branch on co-processor condition instructions as an input port. The SBrCond(2)
input has special internal logic to synchronize the input, and thus may be driven by asynchronous
agents.
If this pin is selected to function as Extended Data Enable, it may be asserted as an output on reads,
writes, or both, as programmed into CP0. This strobe can be used as an extended data enable strobe,
in that it is held asserted for one-half clock cycle after the negation of
be used as a write enable control line for transceivers, as a write line for I/O, or as an address mux select
for DRAMs.
Memory Strobe: This active low output pulses low for each data read or written, as configured in the
CP0 Bus Control register. Thus, it can be used as a read strobe, write strobe, or both, for SRAM type
memories or for I/O devices.
The R3041
MemStrobe
BusGnt
output early, and waiting for the
output pin is designated as the BrCond(0) input pin in the R3051 and R3081.
WrNear
IOStrobe
output tells the external memory system that the bus interface unit
DESCRIPTION
, it may be asserted as an output on reads, writes, or both,
BusReq
Burst
signal indicates that the current bus read
input to be negated.
COMMERCIAL TEMPERATURE RANGE
Rd
or
Wr
. This signal may typically
BusReq
has been
2905 tbl 04
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