IDT79R3041-20J IDT, Integrated Device Technology Inc, IDT79R3041-20J Datasheet - Page 4

• Manufacturer Part Number: IDT79R3041-20J
• Description: IC MPU 32BIT 5V 20MHZ 84-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R3041-20J

• Processor Type: RISC 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R3041-20J

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
Clock Generation Unit
capable of operating in a range of 40%-60% duty cycle. On-
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in R3000A based applications.
Instruction Cache
organized with a line size of 16 bytes (four 32-bit entries) a nd
is direct mapped. This relatively large cache substantially
contributes to the performance inherent in the R3041, and
allows systems based on the R3041 to achieve high-perfor-
mance even from low-cost memory systems. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses and physical tags (rather than virtual addresses or
tags), and thus does not require flushing on context switch.
Data Cache
organized as a line size of 4 bytes (one word) and is direct
mapped. This relatively large data cache contributes substan-
tially to the performance inherent in the RISController family.
As with the instruction cache, the data cache is implemented
as a direct mapped physical address cache. The cache is
capable of mapping any word within the 4GB physical address
space.
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4-
deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.
Bus Interface Unit
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE (Address Latch
Enable) output signal to de-multiplex the A/D bus, and simple
handshake signals to process CPU read and write requests.
In addition to the read and write interface, the R3041 incorpo-
rates a DMA arbiter, to allow an external master to control the
The R3041 is driven from a single 2x frequency input clock,
The R3041 integrates 2kB of on-chip Instruction Cache,
The R3041 incorporates an on-chip data cache of 512B,
The data cache is implemented as a write through cache,
The RISController family uses its large internal caches to
The RISController family bus interface utilizes a 32-bit
external bus.
capability by adding the ability to directly interface with varying
memory port widths, for instructions or data. For example, the
R3041 can be used in a system with an 8-bit boot PROM, 16-
bit font/program cartridges, and 32-bit main memory, trans-
parently to software, and without requiring external data
packing, rotation, and unpacking.
some of the interface timing of the bus. These features can be
used to eliminate external data buffers and take advantage of
lower speed and lower cost interface components.
Hold mode which adds 1/2 clock of extra address hold time
from ALE falling. This allows easier interfacing to FPGAs and
ASICs.
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FIFO proces-
sor address and data information in store operations, and
present it to the bus interface as write transactions at the rate
the memory system can accommodate. During main memory
writes, the R3041 can break a large datum (e.g. 32-bit word)
into a series of smaller transactions (e.g. bytes), according to
the width of the memory port being written. This operation is
transparent to the software which initiated the store, insuring
that the same software can run in true 32-bit memory systems.
single word reads and quad word reads. Single word reads
work with a simple handshake, and quad word reads can
either utilize the simple handshake (in lower performance,
simple systems) or utilize a tighter timing mode when the
memory system can burst data at the processor clock rate.
Thus, the system designer can choose to use page or static
column mode DRAMs (and possibly use interleaving, if de-
sired, in high-performance systems), or even to use simpler
SRAM techniques to reduce complexity.
RISController family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches.
when performing large datum reads (e.g., quad words) from
narrower memory systems (e.g., 16-bits). Once again, this
operation is transparent to the actual software, simplifying
migration of software to higher performance (true 32-bit)
systems, and simplifying field upgrades to wider memory.
Since this capability works for either instruction or data reads,
using 8-, 16-, or 32-bit boot PROMs is easily supported by the
The R3041 augments the basic RISController bus interface
In addition, the R3041 incorporates the ability to change
One of the bus interface options is the Extended Address
The R3041 incorporates a 4-deep write buffer to decouple
The RISController family read interface performs both
In order to accommodate slower quad word reads, the
In addition, the R3041 can perform on-chip data packing
COMMERCIAL TEMPERATURE RANGE
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