IDT79RC32H434-300BC IDT, Integrated Device Technology Inc, IDT79RC32H434-300BC Datasheet - Page 16

• Manufacturer Part Number: IDT79RC32H434-300BC
• Description: IC MPU 32BIT CORE 300MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-300BC

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32H434-300BC

S S S S ystem Clock Parameters
PCLK
ICLK
CLK
Parameter
IDT RC32434
ystem Clock Parameters
ystem Clock Parameters
ystem Clock Parameters
(Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16.)
1.
2.
3.
4.
5.
The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). Refer to Chapter 3, Clocking and Initialization, in the RC32434
The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK <= 1/2(ICLK)).
PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66 MHz.
The input clock (CLK) is input from the external oscillator to the internal PLL.
ICLK is the internal IPBus clock. It is always equal to PCLK divided by 2. This clock cannot be sampled externally.
User Reference Manual for the allowable frequency ranges of CLK and PCLK.
5
2,3,4
1
Symbol
Frequency
Frequency
Frequency
Thigh_5a,
Trise_5a,
Tjitter_5a
Tper_5a
Tlow_5a
Tfall_5a
Tper
Tper
CLK
Reference
Edge
none
none
none
Tjitter_5a
Min
200
100
3.8
7.5
8.0
25
40
—
—
266MHz
Tper_5a
Figure 3 Clock Parameters Waveform
Max
10.0
40.0
266
133
125
5.0
3.0
0.1
60
Table 5 Clock Parameters
Tjitter_5a
Min
200
100
16 of 53
3.3
6.7
8.0
25
40
—
—
300MHz
Max
10.0
40.0
300
150
125
5.0
3.0
0.1
60
Thigh_5a
2.85
Min
200
100
5.7
8.0
25
40
—
—
350MHz
Tlow_5a
Trise_5a
Max
10.0
40.0
350
175
125
5.0
3.0
0.1
60
Min
200
100
2.5
5.0
8.0
25
40
—
—
Tfall_5a
400MHz
Max
10.0
40.0
400
200
125
5.0
3.0
0.1
60
Tper_5a
Units
MHz
MHz
MHz
% of
ns
ns
ns
ns
ns
January 19, 2006
See Figure 3.
Reference
Diagram
Timing