IDT79RC32H434-300BC IDT, Integrated Device Technology Inc, IDT79RC32H434-300BC Datasheet - Page 2

• Manufacturer Part Number: IDT79RC32H434-300BC
• Description: IC MPU 32BIT CORE 300MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-300BC

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32H434-300BC

IDT RC32434
– Provides “glueless” interface to standard SRAM, Flash, ROM,
– Demultiplexed address and data buses: 8-bit data bus, 26-bit
– Flexible protocol configuration parameters: programmable
– Write protect capability per chip select
– Programmable bus transaction timer generates warm reset
– Supports up to 64 MB of memory per chip select
– 6 DMA channels: two channels for PCI (PCI to Memory and
– Provides flexible descriptor based operation
– Supports unaligned transfers (i.e., source or destination
– Compatible with the 16550 and 16450 UARTs
– 16-byte transmit and receive buffers
– Programmable baud rate generator derived from the system
– Fully programmable serial characteristics:
– Line break generation and detection
– False start bit detection
– Internal loopback mode
– Supports standard 100 Kbps mode as well as 400 Kbps fast
– Supports 7-bit and 10-bit addressing
– Supports four modes: master transmitter, master receiver,
– Interrupt controller
– System integrity functions
– General purpose I/O controller
– Serial peripheral interface (SPI)
– Three general purpose 32-bit counter timers
– Timers may be cascaded
– Selectable counter/timer clock source
– Compatible with IEEE Std. 1149.1 - 1990
Memory and Peripheral Device Controller
DMA Controller
Universal Asynchronous Receiver Transmitter (UART)
Additional General Purpose Peripherals
Counter/Timers
JTAG Interface
I
2
C-Bus
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation
dual-port memory, and peripheral devices
address bus, 4 chip selects, control for external data bus
buffers
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
when counter expires
Memory to PCI), two channels for the Ethernet interface, and
two channels for memory to memory DMA operations
address may be on any byte boundary) with arbitrary byte
length
clock
mode
slave transmitter, slave receiver
Automatic byte gathering and scattering
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C C C C PU Execution Cor
set architecture (ISA). Specifically, this device features the 4Kc CPU
core developed by MIPS Technologies Inc. (www.mips.com). This core
issues a single instruction per cycle, includes a five stage pipeline and is
optimized for applications that require integer arithmetic.
caches are 4-way set associative and can be locked on a per line basis,
which allows the programmer control over this precious on-chip memory
resource. The core also features a memory management unit (MMU).
The CPU core also incorporates an enhanced joint test access group
(EJTAG) interface that is used to interface to in-circuit emulator tools,
providing access to internal registers and enabling the part to be
controlled externally, simplifying the system debug process.
range of software and development tools available for the MIPS archi-
tecture, including operating systems, compilers, and in-circuit emula-
tors.
PCI Interface
PCI Interface
PCI Interface
PCI Interface
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32434 to act as a slave controller for a PCI add-in
card application or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32434 device.
Ethernet Interface
Ethernet Interface
Ethernet Interface
Ethernet Interface
100Mbps speeds to provide a standard media independent interface
(MII or RMII), allowing a wide range of external devices to be connected
efficiently.
Double Data Rate Memory Controller
Double Data Rate Memory Controller
Double Data Rate Memory Controller
Double Data Rate Memory Controller
(DDR) memory controller which supports x16 memory configurations up
to 256MB. This module provides all of the signals required to interface
to discrete memory devices, including a chip select, differential clocking
outputs and data strobes.
M M M M emory and I
a de-multiplexed 8-bit data and 26-bit address bus. It includes all of the
signals required to interface directly to a maximum of four Intel or
Motorola-style external peripherals.
PU Execution Cor
PU Execution Cor
PU Execution Core e e e
emory and I
emory and I
emory and I/ / / / O Controlle
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
The CPU core includes 8 KB instruction and 8 KB data caches. Both
The use of this core allows IDT's customers to leverage the broad
The PCI interface on the RC32434 is compatible with version 2.2 of
The RC32434 has one Ethernet Channel supporting 10Mbps and
The RC32434 incorporates a high performance double data rate
The RC32434 uses a dedicated local memory/IO controller including
O Controlle
O Controller r r r
O Controlle
January 19, 2006