IDT79RC32K438-300BBG IDT, Integrated Device Technology Inc, IDT79RC32K438-300BBG Datasheet - Page 18

• Manufacturer Part Number: IDT79RC32K438-300BBG
• Description: IC MPU 32BIT CORE 300MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-300BBG

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32K438-300BBG

AC Timing Definitions
IDT 79RC32438
Below are examples of the AC timing characteristics used throughout this document.
Tper
Tlow
Thigh
Trise
Tfall
Tjitter
Tdo
Tzd
Tdz
Tsu
Thld
Tpw
Tslew
X(clock)
Tskew
Symbol
Clock period.
Clock low. Amount of time the clock is low in one clock period.
Clock high. Amount of time the clock is high in one clock period.
Rise time. Low to high transition time.
Fall time. High to low transition time.
Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges.
Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold.
The maximum time represents the earliest time the designer can use the data.
Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid.
Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated.
Input set-up. Amount of time before the reference clock edge that the input must be valid.
Input hold. Amount of time after the reference clock edge that the input must remain valid.
Pulse width. Amount of time the input or output is active for asynchronous signals.
Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high.
Timing value. This notation represents a value of ‘X’ multiplied by the clock time period of the specified clock. Using 5(CLK) as an example:
X = 5 and the oscillator clock (CLK) = 25MHz, then the timing value is 200.
Skew. The amount of time two signal edges deviate from one another.
Output signal 1
Output signal 2
Input Signal 1
Signal 1
Signal 2
Signal 3
clock
Figure 2 AC Timing Definitions Waveform
Table 4 AC Timing Definitions
Tzd
Tdo
Tskew
Tper
18 of 59
Tsu
Definition
Tdo
Tdz
Thld
Tjitter
Thigh
Thigh
Tpw
Tpw
Tlow
Trise
Tfall
May 25, 2004