PRIXP425BC Intel, PRIXP425BC Datasheet - Page 10

• Manufacturer Part Number: PRIXP425BC
• Description: IC NETWRK PROCESSR 400MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BC

• Processor Type: Network
• Features: XScale Core
• Speed: 400MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869083

Summary Table of Changes
Non-Core Errata (Continued)
Core Errata
10
No.
No.
23
24
25
26
27
28
29
30
31
32
33
34
35
1
2
3
4
Intel
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Steppings
Steppings
®
IXC1100
IXC1100
IXP425
IXP425
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
B0
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
,
,
Steppings
Steppings
B0
B0
IXP420,
IXP421,
X
X
X
X
IXP420,
IXP421,
X
X
X
X
X
X
X
X
X
X
X
X
X
IXP422
IXP422
Page Status
Page Status
30
30
30
31
26
26
26
27
27
27
27
28
28
28
29
29
29
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Ethernet Coprocessors - Length Errors on Received
Frames (SCR 711)
PCI DC Parameter VIH Marginality Issue (SCR 3121)
False PCI DMA Completion Notification Causing Data
Corruption (SCR 3910)
Expansion Bus HPI Interface Potential for Contention on
Reads with T4=0 (SCR 4117)
PCI Hangs With a Multiple Inbound Error Condition
(SCR 4160)
PCI RCOMP Operation if PCI Clock Stops (SCR 4022)
UART - Break Condition Asserted Too Early if Two Stop
bits are Used (SCR 4092)
Ethernet Coprocessors - Address Filtering Logic Ignores
the Second to Last Nibble of the Destination Address
(SCR 4185)
USB DC Parameter VIH Specification Change
(SCR 3111)
Start of DMA Operation Close to Start of Non-Prefetch
(NP) Operation can Hang NP Operation on AHB (SCR
3939)
PCI Accesses to the Queue Manager During Queue and
SRAM Mode (SCR 4076)
Ethernet MACs Detect Late Collision Earlier Than
Ethernet 802.3 Specifications (SCR 4062)
Read of PCI Controllers BAR 32'hXXFF_FFFC Rd[N]
Corrupts Subsequent Rd[N+1] (SCR 3850)
Abort is Missed When Lock Command is Outstanding
Aborted Store That Hits the Data Cache May Mark
Write-Back Data as ‘Dirty’
Performance Monitor Unit Event 0x1 Can Be
Incremented Erroneously by Unrelated Events
In Special Debug State, Back-to-Back Memory
Operations — Where the First Instruction Aborts — May
Cause a Hang
Specification Changes
Errata