PRIXP425BC Intel, PRIXP425BC Datasheet - Page 27

• Manufacturer Part Number: PRIXP425BC
• Description: IC NETWRK PROCESSR 400MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BC

• Processor Type: Network
• Features: XScale Core
• Speed: 400MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869083

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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Expansion Bus HPI Interface Potential for Contention on Reads with T4=0
(SCR 4117)
If any HPI slave on the expansion bus has T4 configured to 0, there is potential for contention on
the data during a read. The HPI specification states that it stops driving data a max of 10 ns after the
deassertion of DS (which is ex_wr_n). The Intel
and IXC1100 Control Plane Processor turns on the output enable in the T4 state, which is the same
cycle where ex_wr_n gets deasserted, so there is no turnaround cycle.
With T4 configured to 0 on any HPI slave in the EXP_TIMING_CS register there could be
contention on EX_DATA for up to 10ns during a read.
The appropriate EXP_TIMING_CS register (each CS with HPI) must have T4 configured to a
non-zero value, which will extend the T4 state for at least one cycle and eliminate the possibility of
contention on EX_DATA.
No
PCI Hangs With a Multiple Inbound Error Condition (SCR 4160)
The PCI controller may lock up if there are multiple errors occurring around two different inbound
PCI transactions. When an inbound PCI read that targets an internal slave such as the Expansion
bus, or Queue Manager, results in an AHB error which occurs due to the PCI controller generating
an illegal AHB transfer type on the target, and a second inbound PCI transfer is started while the
first PCI read is still pending and the second PCI transfer detects a PCI address or data parity error
a lock-up will occur.
The PCI controller will continue to retry all inbound transactions, and the PCI bus will lock up.
When the PCI controller has an AHB error logged (PCI_ISR.AHBE = 1), a PCI parity error logged
(PCI_SRCR.DPE = 1), and the PCI controller retries every inbound transaction, the system board
must reset the IXP42X product line and IXC1100 control plane processors.
No
PCI RCOMP Operation if PCI Clock Stops (SCR 4022)
The PCI specification states that PCI_CLKIN can be any frequency from 0 to 66 MHz, and can
change in frequency at any time. The PCI_CLKIN frequency cannot be changed on the fly on the
IXP42X product line as the AC timing specifications can not be guaranteed.
The IXP42X product line does not support switching between 33 and 66 MHz on the fly because
the AC timing specifications cannot be guaranteed.
No
UART - Break Condition Asserted Too Early if Two Stop bits are Used (SCR
4092)
The break condition is asserted after the time of the first stop bit, even if two stop bits are used.
In the following scenario, a break condition will be raised on valid data:
•
•
•
Fix.
Fix.
Fix.
Never drive PCI_CLKIN < 1 MHz or the PCI AC timings/slew rates will exceed the
specification.
If performing a PCI software reset, wait at least 2 ms after the deassertion of software reset
before using the PCI interface.
To switch between 33 MHz and 66 MHz PCI operation, and to guarantee specified AC
timings, the IXP42X product line must go into reset first, and then change the PCI CLKIN by
pulling up or pulling down the EX_ADDR[4] pin.
®
IXP42X Product Line of Network Processors
Non-Core Errata
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