PRIXP425BC Intel, PRIXP425BC Datasheet - Page 28

• Manufacturer Part Number: PRIXP425BC
• Description: IC NETWRK PROCESSR 400MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BC

• Processor Type: Network
• Features: XScale Core
• Speed: 400MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869083

Non-Core Errata
Workaround:
Status:
30.
Problem:
Implication:
Workaround:
Status:
31.
Problem:
Implication:
Workaround:
Status:
Affected Docs:
32.
Problem:
Implication:
Workaround:
Status:
28
Don't use two stop bits.
No
Ethernet Coprocessors - Address Filtering Logic Ignores the Second to Last
Nibble of the Destination Address (SCR 4185)
The IXP42X product line has an Ethernet coprocessor configured by Intel XScale core software.
[Note that some IXP42X product line have two Ethernet coprocessors.] The Ethernet coprocessor
logic ignores the second last nibble of the destination address regardless of the packet type (unicast,
multicast, broadcast), that is, Destination Address: 11 22 33 44 55 x6. The reason it is the second
last is that the address is transmitted on the line with the high nibble first and then the low nibble.
Some Ethernet frames with the wrong destination address can get through the Address Filter.
A software workaround is possible using the ixEthDb filtering capabilities.
No Fix. See the
USB DC Parameter VIH Specification Change (SCR 3111)
The input-high voltage (VIH) for the USB signals does not meet the documented specification. In
the Intel
Datasheet, Table 26, the USB DC Parameters specifies the VIH minimum value as 2.0 V. This
specification is changed to 2.15 V.
The USB VIH DC parameter does not meet industry-standard specifications.
None
No
Intel
Datasheet (252479-002)
Start of DMA Operation Close to Start of Non-Prefetch (NP) Operation can
Hang NP Operation on AHB (SCR 3939)
If a DMA operation is initiated in close proximity to an outbound NP operation being initiated, the
NP operation may not terminate properly within the PCI Controller, resulting in no further AHB
operations being accepted by the controller (retries issued). This errata only occurs if two different
masters start an NP and DMA operation.
If the NP operation is sent to the PCI Core for execution on the PCI bus, but the DMA engine starts
as well, the DMA should wait until the NP operation is done before proceeding. The active DMA
engine blocks the “cycle complete” indication from the PCI for the NP operation, which leaves the
AHB target interface hung since no other AHB operations can be accepted until the NP operation
completes (retries issued).
Only use PCI DMA/Non-prefetch PCI operations. Additionally, if the processor is starting a PCI
DMA transfer, it must always write to the PCI_NP_AD register before accessing the PCI_NP_CBE
or PCI_NP_WDATA. A dummy CSR read could be performed before the NP operation is initiated.
This would separate the NP op initiation from a previously started DMA
No
1. A byte consisting only of zeros is received.
2. The first stop bit sampling is missed, and only the second one is sampled.
Fix.
Fix.
Fix.
®
Intel
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
“Summary Table of Changes” on page
8.