A80960CA25 Intel, A80960CA25 Datasheet - Page 13

• Manufacturer Part Number: A80960CA25
• Description: IC MPU I960CA 25MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CA25

• Processor Type: i960
• Features: CA suffix, 32-Bit with DMA, 1K Cache
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 802884

CLKIN
CLKMODE
PCLK2:1
V
V
V
NC
SS
CC
CCPLL
Name
Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 2 of 2)
Type
H(Q)
R(Q)
A(E)
H(Z)
R(Z)
H(Z)
R(Z)
A(L)
O
S
–
–
–
–
I
I
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
CLOCK MODE selects the division factor applied to the external clock input
(CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and
the processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to
create PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high
or low in a system as the clock mode is not latched by the processor. If left
unconnected, the processor will internally pull the CLKMODE pin low, enabling the
2-x clock mode.
PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor
inputs and outputs. All input and output timings are specified in relation to PCLK2
and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided
to allow flexibility in the system’s allocation of capacitive loading on the clock.
PCLK2:1 may also be connected at the processor to form a single clock signal.
GROUND connections must be connected externally to a V
POWER connections must be connected externally to a V
V
Connecting a simple lowpass filter to V
noisy environments. Otherwise, V
implemented starting with the D-stepping. See Table 13 for die stepping
information.
NO CONNECT pins must not be connected in a system.
CCPLL
is a separate V
CC
supply pin for the phase lock loop used in 1-x clock mode.
CCPLL
Description
CCPLL
should be connected to V
may help reduce clock jitter (T
CC
80960CA-33, -25, -16
SS
board plane.
board plane.
CC
. This pin is
CP
) in
9