A80960CA25 Intel, A80960CA25 Datasheet - Page 63

• Manufacturer Part Number: A80960CA25
• Description: IC MPU I960CA 25MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CA25

• Processor Type: i960
• Features: CA suffix, 32-Bit with DMA, 1K Cache
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 802884

Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge
PCLK2:1
EOP
(All Modes)
Note:
1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus
PCLK2:1
(Case 1)
(Case 2)
! (BLAST
& READY
& !WAIT)
DREQx
DREQx
triggered. EOP must be
DACKx
unpacking modes in which loads are followed by loads or stores are followed by stores.
Applications are non Fly-By transfers and adjacent load-stores or store-loads.
accesses (defined by ADS and BLAST. Refer to i960 Cx Microprocessor User’s Manual for “access”,
“request” definitions.
ADS
2 CLKs Min
Figure 43. DREQ and DACK Functional Timing
held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.
(See Note)
Figure 44. EOP Functional Timing
High To Prevent
Next Bus Cycle
t
IS5
15 CLKs Max
t
IH5
High To Prevent
Next Bus Cycle
t
IS5
t
IH5
80960CA-33, -25, -16
System
Clock
Start DMA
Bus Request
End of DMA
Bus Request
DMA
Acknowledge
DMA
Request
F_CX045A
F_CX018A
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