A80960CA25 Intel, A80960CA25 Datasheet - Page 3

• Manufacturer Part Number: A80960CA25
• Description: IC MPU I960CA 25MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CA25

• Processor Type: i960
• Features: CA suffix, 32-Bit with DMA, 1K Cache
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 802884

CONTENTS
LIST OF FIGURES
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Figure 38
80960CA Block Diagram .............................................................................................................. 1
80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13
80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14
80960CA PQFP Pinout (View from Top Side) ............................................................................ 17
Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18
Register g0 ................................................................................................................................. 20
AC Test Load .............................................................................................................................. 29
Input and Output Clocks Waveform ............................................................................................ 29
CLKIN Waveform ........................................................................................................................ 29
Output Delay and Float Waveform ............................................................................................. 30
Input Setup and Hold Waveform ................................................................................................ 30
NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31
Hold Acknowledge Timings ........................................................................................................ 31
Bus Backoff (BOFF) Timings ...................................................................................................... 32
Relative Timings Waveforms ...................................................................................................... 33
Output Delay or Hold vs. Load Capacitance .............................................................................. 33
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
I
Cold Reset Waveform ................................................................................................................ 36
Warm Reset Waveform .............................................................................................................. 37
Entering the ONCE State ........................................................................................................... 38
Clock Synchronization in the 2-x Clock Mode ............................................................................ 39
Clock Synchronization in the 1-x Clock Mode ............................................................................ 39
Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40
Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41
Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51
Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52
Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53
Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54
CC
vs. Frequency and Temperature ........................................................................................... 34
CC
.................. 34
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