A80960CA25 Intel, A80960CA25 Datasheet - Page 8

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A80960CA25

Manufacturer Part Number
A80960CA25
Description
IC MPU I960CA 25MHZ 168-PGA
Manufacturer
Intel
Datasheet

Specifications of A80960CA25

Processor Type
i960
Features
CA suffix, 32-Bit with DMA, 1K Cache
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
168-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
802884

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A80960CA25
Manufacturer:
MAXIM
Quantity:
180
80960CA-33, -25, -16
3.0
3.1
This section describes the pins, pinouts and thermal
characteristics for the 80960CA in the 168-pin
Ceramic Pin Grid Array (PGA) package and the 196-
pin Plastic Quad Flat Package (PQFP). For complete
package specifications and information, see the
Packaging Handbook (Order No. 240800).
3.2
The 80960CA pins are described in this section.
Table 2 presents the legend for interpreting the pin
descriptions in the following tables. Pins associated
with the 32-bit demultiplexed processor bus are
described in Table 3. Pins associated with basic
processor configuration and control are described in
Table 4. Pins associated with the 80960CA DMA
Controller and Interrupt Unit are described in Table
5.
All pins float while the processor is in the ONCE
mode.
4
PACKAGE INFORMATION
Package Introduction
Pin Descriptions
Symbol
S(...)
A(...)
H(...)
R(...)
I/O
O
I
Table 2. Pin Description Nomenclature
Input only pin
Output only pin
Pin can be either an input or output
Pins “must be” connected as described
Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. All outputs are
synchronous to PCLK2:1.
Asynchronous. Inputs may be
asynchronous to PCLK2:1.
While the processor’s bus is in the
Hold Acknowledge or Bus Backoff state,
the pin:
While the processor’s RESET pin is low,
the pin:
S(E)
S(L)
A(E)
A(L)
H(1)
H(0)
H(Z)
H(Q)
R(1)
R(0)
R(Z)
R(Q)
Edge sensitive input
Level sensitive input
Edge sensitive input
Level sensitive input
is driven to V
is driven to V
floats
continues to be a valid output
is driven to V
is driven to V
floats
continues to be a valid input
Description
CC
SS
CC
SS

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