CS42L55-DNZ Cirrus Logic Inc, CS42L55-DNZ Datasheet - Page 34

• Manufacturer Part Number: CS42L55-DNZ
• Description: IC CODEC STER H-HDPN AMP 36-QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L55-DNZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 99
• Voltage - Supply, Analog: 1.65 V ~ 2.71 V
• Voltage - Supply, Digital: 1.65 V ~ 2.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1506 - BOARD EVAL FOR CS42L55 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

34
4.8
4.9
4.10
SDOUT
LRCK
SCLK
SDIN
Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in Slave Mode (M/S = ‘0’b) and will generate synchronous clocks derived from an input master clock
(MCLK) in Master Mode (M/S = ‘1’b). Refer to the table below for the required setting in register 05h asso-
ciated with a given MCLK and sample rate.
Digital Interface Format
The serial port operates in the I²S digital interface formats with varying bit depths up to 24 into the DAC and
a fixed depth of 24 out the ADC. Data is clocked out of the ADC on an internally delayed version of the rising
SCLK edge. This provides more setup time for capturing data on the rising edge of SCLK. Data is clocked
into the DAC on the rising edge of SCLK.
Initialization
The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, del-
ta-sigma modulators and control port registers are reset. The charge pump, LDO, internal voltage reference
and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state
until the RESET pin is brought high. The control port is accessible once RESET is high and the desired reg-
ister settings can be loaded per the interface descriptions in the
Referenced Control
Register 05h ........................
M/S ......................................
(MCLKDIV2=’1’b)
(MCLKDIV2=’0’b)
MCLK (MHz)
M S B
12.0000
6.0000
AOUTA / AINxA
L eft C h a n n el
LRCK (kHz) Clock Ratio SPEED[1:0] 32kGROUP RATIO[1:0] Register 05h
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1180
48.0000
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1180
48.0000
Register Location
“Clocking Control 2 (Address 05h)” on page 44
“Master/Slave Mode” on page 43
8.0000
8.0000
Figure 20. I²S Format
L S B
187.5
1500
1088
1000
750
544
500
375
272
250
750
544
500
375
272
250
136
125
M S B
10
10
10
01
01
01
10
10
10
01
01
01
11
11
11
11
11
11
“Register Description” on page
AOUTB / AINxB
R ig ht C h a n n el
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
01
01
01
01
01
01
01
01
01
01
01
01
11
11
11
11
11
11
L S B
CS42L55
42.
0x1D
0x0D
0x1D
0x0D
0x1B
0x0B
0x1B
0x0B
0x19
0x15
0x13
0x11
0x09
0x19
0x15
0x13
0x11
0x09
DS773F1
M S B