CS42416-DQZR Cirrus Logic Inc, CS42416-DQZR Datasheet - Page 34

• Manufacturer Part Number: CS42416-DQZR
• Description: IC CODEC 6CH 110DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42416-DQZR

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 110
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC, 6 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

34
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
ADC Mode
Set DAC_FMx = 00,01,10
Set ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 0 or 1
Set ADC_OLx bits = 00
Set DAC_OLx bits = 00,01,10
Set DAC_SP M/S = 0 or 1
Set ADC_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
Set DIFx bits to proper serial format
4.5.4.4
This One-Line Mode configuration can support up to 6 channels of DAC data on 2 DAC_SDIN pins and 2
channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all chan-
nels for both the DAC and ADC. The output data stream of the internal ADCs can be configured to run at
the DAC_SP clock speeds or to run at the ADC_SP rate. The DAC_SP and ADC_SP can operate at differ-
ent Fs rates.
Register / Bit Settings
Line Mode
One-Line
One-Line
Not One-
Mode #1
Mode #2
OLM Config #4
DAC_SCLK=64Fs/128Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
Not One-Line Mode
RMCK
ADCIN1
ADCIN2
not valid
not valid
CS42416
Figure 20. OLM Configuration #4
ADC_SDOUT
DAC_SCLK
DAC_LRCK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
ADC_LRCK
ADC_SCLK
64Fs,128Fs, 256Fs
Set ADC operating mode to Not One-Line Mode since only 2 channels of
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
64Fs,128Fs
Configure ADC_SDOUT to be clocked from the ADC_SP or DAC_SP
Select the digital interface format when not in One-Line Mode
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
Select DAC operating mode, see table below for valid combinations
External ADCs are not used. Leave bit in default state.
Set DAC Serial Port to Master Mode or Slave Mode.
Set ADC Serial Port to Master Mode or Slave Mode.
One-Line Mode #1
SDIN_PORT1
LRCK_PORT2
M CLK
SCLK_PORT1
LRCK_PORT1
SDIN_PORT2
SCLK_PORT2
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
DAC Mode
DIGITAL AUDIO
PROCESSOR
not valid
not valid
ADC are supported
Description
clocks.
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
One-Line Mode #2
not valid
not valid
CS42416
DS602F1