IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 68
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IDTSTAC9753AXNAED1XR
Manufacturer Part Number
IDTSTAC9753AXNAED1XR
Description
IC CODEC AC'97 MIC/JACK 32-QFN
Manufacturer
IDT, Integrated Device Technology Inc
Type
Audio Codec '97r
Datasheet
1.IDTSTAC9752AXNAED1XR.pdf
(106 pages)
Specifications of IDTSTAC9753AXNAED1XR
Resolution (bits)
20 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
85 / 92
Voltage - Supply, Analog
3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-QFN
Single Supply Voltage (typ)
3.3/5V
Single Supply Voltage (min)
3.135V
Single Supply Voltage (max)
3.465/5.25V
Package Type
VFQFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
STAC9753AXNAED1XR
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
7.2.
7.1.24.
7.2.1.
General Purpose Input & Outputs
15 in 2.3
Bit(s)
13:12
10:4
14
11
3
2
1
0
CC3
D15
D7
V
SPDIF Control (3Ah)
Default: 2000h
EAPD
EAPD can act as a GPIO, but is unaffected by the following registers. To use EAPD as a GPIO, use
Register 74h, the EAPD Access Register. Information about this register is located in Section
page63.
7.4.11: page82. Additional information about EAPD can also be found in Section 7.1.18.3:
Reset Value
10
0
0
0
0
0
0
0
DRS
CC2
D14
D6
Read & Write SPSR[1,0]
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read Only
Access
SPSR1
CC1
D13
D5
CC[6, 0]
/AUDIO
COPY
Name
PRO
DRS
PRE
V
L
SPSR2
CC0
D12
68
D4
Validity: This bit affects the "Validity" flag, bit<28>, transmitted in
each S/PDIF subframe, and enables the S/PDIF transmitter to
maintain connection during error or mute conditions. Subframe
bit<28>=0 indicates that data is valid for conversion at the
receiver, 1 indicates invalid data (not suitable for conversion at
the receiver).
If “V” = 1, then each S/PDIF subframe (Left & Right) should have
bit<28> “Validity” flag = 1 or set based on the assertion or
de-assertion of the AC '97 “VFORCE” bit within the Extended
Audio Status and Control Register (D15, register 2Ah).
1 = Double Rate SPDIF support (always = 0)
SPDIF Sample Rate.
00 - 44.1 KHz Rate
01 - Reserved
10 - 48 KHz Rate (default)
11 - 32 KHz Rate
Generation Level is defined by the IEC standard, or as
appropriate.
Category Code is defined by the IEC standard or as appropriate
by media.
0 = 0 sec Pre-emphasis
1 = Pre-emphasis is 50/15 sec
0 = Copyright not asserted
1 = Copyright is asserted
0 = PCM data
1 = Non-Audio or non-PCM format
0 = Consumer use of the channel
1 = Professional use of the channel
PRE
D11
D3
L
Description (note 1-2)
STAC9752A/9753A
COPY
CC6
D10
D2
/AUDIO
CC5
D9
D1
PC AUDIO
PRO
CC4
V 1.5 1206
D8
D0