IDTSTAC9752AXNAED1X IDT, Integrated Device Technology Inc, IDTSTAC9752AXNAED1X Datasheet - Page 28

• Manufacturer Part Number: IDTSTAC9752AXNAED1X
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9752AXNAED1X

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9752AXNAED1X

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
4.5.
4.6.
4.5.1.
4.6.1.
STAC9752A/9753A as a Primary CODEC
AC-Link Power Management
The following are potential 24.576MHz clock options available to a Secondary CODEC:
•
•
•
Primary devices are required to support correctly either of the following clocking options:
•
•
•
The Primary device may also optionally support the following clocking option:
•
STAC9752A/9753A as a Secondary CODEC
Secondary devices are required to function correctly using one or more of the following clocking
options:
•
•
Powering down the AC-Link
The AC-Link signals can be placed in a low power mode. When AC‘97’s Powerdown Register (26h)
is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a
logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not attempt to
play or capture audio data until it has sampled a CODEC Ready indication from AC‘97.
See section 2.2.4: page17 for clock frequencies supported and configurations.
See section 2.2.4: page17 for clock frequencies supported and configurations.
See section 2.2.4: page17 for clock frequencies supported and configurations.
Using an external 24.576 MHz signal source (external oscillator or AC‘97 Digital Controller)
Using the Primary’s crystal out
Using the Primary’s BIT_CLK output to derive 24.576MHz
24.576MHz crystal attached to XTAL_IN and XTAL_OUT
24.576MHz external oscillator provided to XTAL_IN
12.288MHz oscillator provided to the BIT_CLK input
24.576MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary
24.576MHz clock)
BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored.
14.318MHz external oscillator provided to XTAL_IN
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STAC9752A/9753A
PC AUDIO
V 1.5 1206