IDT821054APF IDT, Integrated Device Technology Inc, IDT821054APF Datasheet - Page 15

• Manufacturer Part Number: IDT821054APF
• Description: IC PCM CODEC QUAD MPI 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054APF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054APF

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
3
3.1
and coefficient RAM. A Channel Program Enable register (GREG6) is
provided for addressing individual or multiple channels. The CE[3:0] bits
in this register are assigned to Channel 4 to Channel 1 respectively. The
channels are enabled to be programmed by setting their respective CE
bits to ‘1’. If two or more channels are enabled, the successive write
commands will be effective to all enabled channels. A broadcast mode
can be implemented by simply enabling all four channels before
performing other write-operation. The broadcast mode is very useful for
configuring the coefficient RAM of the IDT821054A in a large system.
But for read operations, multiple addressing is not allowed.
from other devices in the system. When being read, the IDT821054A will
output an Identification Code of 81H first to indicate that the following
data bytes are from the IDT821054A.
3.1.1
the specified channel(s).
of all four channels.
(Coe-RAM).
to specify the address of the local registers and global registers
respectively.
Coe-RAM.
3.1.2
channel(s) will be addressed first. If two or more channels are specified
via GREG6, the corresponding local registers of the specified channels
will be addressed by a Local Command at the same time.
method for accessing the local registers. According to the address
specified in a Local Command, there will be 1 to 4 adjacent local
R/W
The IDT821054A is programmed by writing commands to registers
The IDT821054A uses an Identification Code to distinguish itself
The IDT821054A provides three types of commands as follows:
Local Command (LC), which is used to address the local registers of
Global Command (GC), which is used to address the global registers
RAM Command (RC), which is used to address the coefficient RAM
The format of the command is as the following:
R/W:
CT:
Address: b[4:0], specify one or more local/global registers or a block
For Local Command and Global Command, the b[4:0] bits are used
For RAM Command, b[4:0] bits are used to specify the block of the
When addressing the local registers, users must specify which
The IDT821054A provides a consecutive adjacent addressing
b7
OPERATING THE IDT821054A
PROGRAMMING DESCRIPTION
COMMAND TYPE AND FORMAT
ADDRESSING THE LOCAL REGISTERS
b6
Read/Write Command bit
b7 = 0:
b7 = 1:
Command Type
b6 b5 = 00: LC - Local Command
b6 b5 = 01: GC - Global Command
b6 b5 = 10: Not Allowed
b6 b5 = 11: RC - RAM Command
of Coe-RAM to be addressed.
CT
b5
Read Command
Write Command
b4
b3
Address
b2
b1
b0
15
registers to be addressed automatically, with the highest order first. For
example, if the address specified in a Local Command ends with ‘11’
(b1b0 = 11), 4 adjacent registers will be addressed by this command; if
b1b0 = 10, 3 adjacent registers will be addressed. See
details.
Table - 1 Consecutive Adjacent Addressing
adjacent addressing can be stopped by the CS signal at any time. If CS
is changed from low to high, the operation to the current register and the
next adjacent registers will be aborted. However, the previous operation
results will not be affected.
3.1.3
specify the channel(s) before addressing a global register. Except for
this, the global registers are addressed in a similar way as local
registers. The procedure of consecutive adjacent addressing can be
stopped by the CS signal at any time.
3.1.4
blocks. Each block consists of 8 words. Each word is 14-bit wide.
coefficients as shown below (refer to
RAM Mapping”
Matching Filter coefficient.
Cancellation Filter coefficient.
(Word 20 - Word 23), containing the Gain of Impedance Scaling and
dual tone coefficients.
containing the coefficient of the Frequency Response Correction in
Transmit Path and the Gain in Transmit Path;
containing the coefficient of the Frequency Response Correction in
Receive Path and the Gain in Receive Path.
GTX, FRR and GRX coefficients are shared by all four channels. When
coefficients are written to these blocks, they will be used by all four
channels. But the four words (word 20 to 23), which contain the dual
(b1b0 = 10, three bytes of data)
Address Specified in a Local
(b1b0 = 11, four bytes of data)
(b1b0 = 01, two bytes of data)
(b1b0 = 00, one byte of data)
When addressing local registers, the procedure of consecutive
For global registers are shared by all four channels, it is no need to
The 5 blocks of the Coe-RAM are assigned for different filter
Block 1: IMF RAM (Word 0 - Word 7), containing the Impedance
Block 2: ECF RAM (Word 8 - Word 15), containing the Echo
Block 3: GIS RAM (Word 16 - Word 19) and Tone Generator RAM
Block 4: FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31),
Block 5: FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39),
The Coe-RAM blocks used for containing the IMF, ECF, GIS, FRX,
There are totally 40 words of Coe-RAM. They are divided to 5
b[4:0] = XXX11
b[4:0] = XXX10
b[4:0] = XXX01
b[4:0] = XXX00
ADDRESSING THE GLOBAL REGISTERS
ADDRESSING THE COE-RAM
Command
for the address of the Coe-RAM):
In/Out Data
Bytes
byte 1
byte 2
byte 3
byte 4
byte 1
byte 2
byte 3
byte 1
byte 2
byte 1
INDUSTRIAL TEMPERATURE
“9 Appendix: IDT821054A Coe-
Registers to be accessed
Address of the Local
XXX10
XXX01
XXX00
XXX10
XXX01
XXX00
XXX01
XXX00
XXX00
XXX11
Table - 1
for