IDT821054APF IDT, Integrated Device Technology Inc, IDT821054APF Datasheet - Page 16

• Manufacturer Part Number: IDT821054APF
• Description: IC PCM CODEC QUAD MPI 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054APF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054APF

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
tone coefficients, can only be addressed on a per-channel basis.
Therefore, users should specify a channel (by setting the corresponding
CE bit in GREG6 to ‘1’) before writing/reading tone coefficients to/from
the Coe-RAM.
needed to fulfill with MSB first, but the lowest two bits (b[1:0]) will be
ignored. When read, each word will output 16 bits with MSB first, but the
lowest two bits (b[1:0]) are meaningless.
3.1.5
3.1.5.1
3.1.5.2
3.1.5.3
coefficients are shared by all four channels. When coefficients are written to these blocks, they will be used by all four channels. But the four words
(word 20 to 23), which contain the tone coefficients, can only be addressed on a per-channel basis. Therefore, users should specify a channel before
writing/reading tone coefficients to/from the Coe-RAM.
To write a Coe-RAM word, 16 bits (b[15:0]) or two 8-bit bytes are
The address in a Coe-RAM command (b[4:0]) specifies a block of
• Writing to LREG2 and LREG1 of Channel 1:
1010, 0101
0001, 0010
1000, 0001
xxxx, xxxx
xxxx, xxxx
• Reading from LREG2 and LREG1 of Channel 1:
1010, 0101
0001, 0010
0000, 0001
After the preceding commands are executed, data will be sent out as follows:
1000, 0001
xxxx, xxxx
xxxx, xxxx
• Writing to GREG1:
1010, 0000
1111, 1111
• Reading from GREG1:
0010, 0000
After the preceding command is executed, data will be sent out as follows:
1000, 0001
0000, 0001
As described in
• Writing to the Coe-RAM
− Examples for Coe-RAM blocks shared by all four channels:
1110,0000
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
data byte 9
data byte 10
data byte 11
data byte 12
data byte 13
PROGRAMMING EXAMPLES
Example of Programming Local Registers
Example of Programming Global Registers
Example of Programming the Coefficient-RAM
Channel Enable command
Data for GREG6 (Channel 1 is enabled for programming)
Local register write command (The address is '00001', which means that data will be written to LREG2 and LREG1.)
Data for LREG2
Data for LREG1
Channel Enable command
Data for GREG6 (Channel 1 is enabled for programming)
Local register read command (The address is '00001', which means that LREG2 and LREG1 will be read.)
Identification code
Data read out from LREG2
Data read out from LREG1
Global register write command (The address is '00000', which means that data will be written to GREG1.)
Data for GREG1
Global register read command (The address is '00000', which means that GREG1 will be read.)
Identification code
Data read out from GREG1
Coe-RAM write command (The address of '00000' is located in block 1, which means that data will be written to block 1.)
high byte of word 8 of block 1
low byte of word 8 of block 1
high byte of word 7 of block 1
low byte of word 7 of block 1
high byte of word 6 of block 1
low byte of word 6 of block 1
high byte of word 5 of block 1
low byte of word 5 of block 1
high byte of word 4 of block 1
low byte of word 4 of block 1
high byte of word 3 of block 1
low byte of word 3 of block 1
high byte of word 2 of block 1
“3.1.4 Addressing the
Coe-RAM”, the Coe-RAM blocks used for containing the IMF, ECF, GIS, FRX, GTX, FRR and GRX
16
Coe-RAM to be accessed. When a Coe-RAM command is executed, the
CODEC automatically counts down from the highest address to the
lowest address of the specified block. So all 8 words of the block will be
addressed by one Coe-RAM command.
adjacent addressing can be stopped by the CS signal at any time. If the
CS signal is changed from low to high, the operation to the current word
and the next adjacent words will be aborted. However, the previous
operation results will not be affected.
When addressing the Coe-RAM, the procedure of consecutive
INDUSTRIAL TEMPERATURE