IDT821054PQF IDT, Integrated Device Technology Inc, IDT821054PQF Datasheet - Page 12

• Manufacturer Part Number: IDT821054PQF
• Description: IC PCM CODEC QUAD MPI 64-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054PQF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054PQF

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
2.2.4
the echo cancellation meets the ITU-T specifications. If the CS[1] bit in
LREG1 is ‘0’, the ECF filter is disabled. If the CS[1] bit is ‘1’, the ECF
coefficient is programmed by the coefficient RAM.
2.2.5
correct any frequency distortion caused by the impedance matching
filter. They are the Frequency Response Correction in the Transmit path
filter (FRX) and the Frequency Response Correction in the Receive path
filter (FRR). If the CS[4] bit in LREG1 is ‘0’, the FRX filter is disabled. If
the CS[4] bit is ‘1’, the FRX coefficient is programmed by the coefficient
RAM. If the CS[6] bit in LREG1 is ‘0’, the FRR filter is disabled. If the
CS[6] bit is ‘1’, the FRR coefficient is programmed by the coefficient
RAM.
address of the GTX, GRX, FRX, FRR, GIS, ECF and IMF coefficients.
2.3
channel: 2 inputs SI1 and SI2, 3 I/Os SB1 to SB3, and 2 outputs SO1
and SO2.
2.3.1
channels or locally for each individual channel.
register GREG9. The SIA[3:0] bits in this register represent the
debounced SI1 data of Channel 4 to Channel 1. The SIB[3:0] bits in this
register represent the debounced SI2 data of Channel 4 to Channel 1.
ground key signals or other signals. The global register GREG9
provides a more efficient way to obtain time-critical data such as on/off-
hook and ring trip information from the SLIC input pins SI1 and SI2.
corresponding local register LREG4.
2.3.2
output via global register GREG10. The SB1C[3:0] bits in GREG10
determine the SB1 directions of Channel 4 to Channel 1: ‘0’ means input
and '1' means output. The SB2C[3:0] bits in GREG11 and the SB3C[3:0]
bits in GREG12 respectively determine the SB2 and SB3 directions of
Channel 4 to Channel 1 in the same way.
read from both global and local registers. The SB1[3:0], SB2[3:0] and
SB3[3:0] bits in global registers GREG10, GREG11 and GREG12
respectively contain the information of SB1, SB2 and SB3 for all four
channels. Users can also read the information of SB1, SB2 and SB3 of
the specified channel from local register LREG4.
only be written to them via GREG10, GREG11 and GREG12
respectively.
The ECF filter is used to adjust transhybrid balance and ensure that
The IDT821054 provides two filters that can be programmed to
Refer to
The SLIC control interface of the IDT821054 consists of 7 pins per
The SLIC inputs SI1 and SI2 can be read in 2 ways - globally for all 4
The SI1 and SI2 status of all 4 channels can be read via global
Both the SI1 and SI2 pins can be connected to off-hook, ring trip,
The SI1 and SI2 status of each channel can also be read via the
The SLIC I/O pin SB1 of each channel can be configured as input or
If the SB1, SB2 or SB3 pin is selected as input, its information can be
If the SB1, SB2 and SB3 pins are configured as outputs, data can
TRANSHYBRID BALANCE
FREQUENCY RESPONSE CORRECTION
SLIC CONTROL
SI1 AND SI2
SB1, SB2 AND SB3
“9 Appendix: IDT821054 Coe-RAM Mapping”
for the
12
2.3.3
SO2 by local register LREG4 on a per-channel basis. When being read,
the SO1 and SO2 bits in LREG4 will be read out with the data written to
them in the previous write operation.
2.4
IDT821054 provides a hardware ring trip function to respond to the off-
hook signal as fast as possible. This function is enabled by setting the
RTE bit in GREG8 to ‘1’.
ring control signal can be output via any of the SO1, SO2, SB1, SB2 and
SB3 pins (assume that SB1-SB3 are configured as outputs). The IS bit
in GREG8 is used to select an input pin and the OS[2:0] bits are used to
select an output pin.
SI2), the IDT821054 will turn off the ring signal by inverting the logic
level of the selected output pin (SO1, SO2, SB1, SB2 or SB3),
regardless of the value of the corresponding SLIC output control register
(the value should be changed later). This function provides a much
faster response to off-hook signals than the software ring trip which
turns off the ring signal by changing the value of the corresponding
register.
pin. If the off-hook signal is active low, the IPI bit should be set to ‘0’. If
the off-hook signal is active high, the IPI bit should be set to ‘1’. The OPI
bit in GREG8 is used to indicate the valid polarity of the output pin. If the
ring control signal is required to be low in normal status and high to
activate a ring, the OPI bit should be set to ‘1’. If it is required to be high
in normal status and low to activate a ring, the OPI bit should be set to
‘0’.
low and ring control signal is active high, the IPI bit should be set to ‘0’
and the OPI bit should be set to ‘1’. In normal status, the selected input
(off-hook signal) is high and the selected output (ring control signal) is
low. When the ring is activated by setting the output (ring control signal)
to high, a low pulse appearing on the input (off-hook signal) will inform
the device to invert the output to low and cut off the ring signal.
2.5
SLIC input state. Each change of the SLIC input state will generate an
interrupt.
SB3 are configured as inputs) can be an interrupt source. As SI1 and
SI2 signals are debounced while the SB1 to SB3 signals are not, users
should pay more attention to the interrupt sources of SB1 to SB3.
bit of IE[4:0] in LREG2 corresponds to one interrupt source of the
specified channel. When one bit of IE[4:0] is ‘0’, the corresponding
interrupt is ignored (disabled), otherwise, the corresponding interrupt is
recognized (enabled).
interrupts can be cleared simultaneously by executing a write operation
to global register GREG2. Additionally, the interrupts caused by all four
The control data can only be written to the two output pins SO1 and
In order to avoid the damage caused by high voltage ring signal, the
The off-hook signal can be input via either SI1 or SI2 pin, while the
When a valid off-hook signal arrives at the selected input pin (SI1 or
The IPI bit in GREG8 is used to indicate the valid polarity of the input
Here is an example: In a system where the off-hook signal is active
An interrupt mechanism is provided in the IDT821054 for reading the
Any of the SLIC inputs including SI1, SI2, SB1, SB2 and SB3 (if SB1-
Local register LREG2 is used to enable/disable the interrupts. Each
Multiple interrupt sources can be enabled at the same time. All
SO1 AND SO2
HARDWARE RING TRIP
INTERRUPT AND INTERRUPT ENABLE
INDUSTRIAL TEMPERATURE RANGE