IDT821054PQF IDT, Integrated Device Technology Inc, IDT821054PQF Datasheet - Page 13

• Manufacturer Part Number: IDT821054PQF
• Description: IC PCM CODEC QUAD MPI 64-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054PQF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054PQF

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
channels’ SI1 and SI2 status changes can be cleared by applying a read
operation to GREG9. If SB1, SB2 and SB3 pins are configured as
inputs, a read operation to GREG10, GREG11 and GREG12 clears the
interrupt generated by the corresponding SB port of all four channels. A
read operation to LREG4 clears all 7 interrupt sources of the specified
channel.
2.6
circuits: Debounced Switch Hook (DSH) Filter for the SI1 signal and
Ground Key (GK) Filter for the SI2 signal. See
two debounce filters are used to buffer the input signals on SI1 and SI2
pins before changing the state of the SLIC Debounced Input SI1/SI2
Register (GREG9). The Frame Sync (FS) signal is necessary for both
DSH and GK filters.
period of the SI1 input of the corresponding channel. The DSH filter is
initially clocked at half of the frame sync rate (250
changing at this sample rate resets a counter that clocks at the rate of 2
ms. The value of the counter is programmable from 0 to 30 via LREG3.
2.7
CHCLK1 and CHCLK2. They can be used to drive the power supply
switching regulators on SLICs. The two chopper clocks are synchronous
to MCLK. The CHCLK1 outputs a signal which clock cycle is
programmable from 2 to 28 ms. The CHCLK2 outputs a signal which
frequency can be 256 kHz, 512 kHz or 16.384 MHz. The frequencies of
the two chopper clocks are programmed by global register GREG5.
2.8
tone generator 1) for each channel. They can produce signals such as
test tone, DTMF, dial tone, busy tone, congestion tone and Caller-ID
Alerting Tone, and output it to the VOUT pin.
For each channel, the IDT821054 provides two debounce filter
The DSH[3:0] bits in LREG3 are used to program the debounce
The IDT821054 provides two programmable chopper clock outputs
The IDT821054 provides two tone generators (tone generator 0 and
DEBOUNCE FILTERS
CHOPPER CLOCK
DUAL TONE AND RING GENERATION
4 kHz
FS/2
SI1
SI2
Debounce
(0-30 ms)
GK[3:0]
Interval
D
Q
7 bit Debounce
Figure - 5
D
Counter
Q
for details. The
µ
s). Any data
Figure - 5 Debounce Filter
Up/down
up/
down
6 states
Counter
D
Q
Q
13
The debounced SI1 signals of Channel 4 to 1 are written to the SIA[3:0]
bits in GREG9. The corresponding SIA bit will not be updated until the
value of the counter is reached. The SI1 pin usually contains the SLIC
switch hook status.
interval of the SI2 input of the corresponding channel. The debounced
SI2 signals of Channel 4 to 1 are written to the SIB[3:0] bits in GREG9.
The GK debounce filter consists of a six-state up/down counter that
ranges between 0 and 6. This counter is clocked by the GK timer at the
sampling period of 0-30 ms, which is programmed via LREG3. If the
sampled value is low, the value of the counter will be decremented by
each clock pulse. If the sampled value is high, the value of the counter is
incremented by each clock pulse. When the value increases to 6, it sets
a latch whose output is routed to the corresponding SIB bit. If the value
decreases to 0, the latch will be cleared and the output bit will be set to
0. In other cases, the latch and the SIB status remain in their previous
state without being changed. In this way, at least six consecutive GK
clocks with the debounce input remaining at the same state can effect
an output change.
the TEN0 and TEN1 bits in LREG10 to ‘1’respectively.
the Coe-RAM. The frequency and amplitude coefficients are calculated
by the following formulas:
parameter of the amplitude. The range of 'A' is from 0 to 1.
A=β ( 0<β<1), the amplitude will be 1.57 ∗ β (V).
tolerances are as the following:
The GK[3:0] bits in LREG3 are used to program the debounce
The dual tone generators of each channel can be enabled by setting
The frequency and amplitude of the tone signal are programmed by
Frequency coefficient = 32767∗ cos(f / 8000 ∗ 2 ∗ π)
Amplitude coefficient = A ∗ 32767 ∗ sin(f / 8000 ∗ 2 ∗ π)
Herein, 'f' is the desired frequency of the tone signal, 'A' is the scaling
A = 1, corresponds to the maximum amplitude of 1.57 V.
A = 0, corresponds to the minimum amplitude of 0 V.
It is a linear relationship between 'A' and the amplitude. That is, if
The frequency range is from 25 Hz to 3400 Hz. The frequency
25 Hz < f < 40 Hz, tolerance < ±12%
Debounce
DSH[3:0]
(0-30 ms)
D
Period
Q
= 0
≠ 0
GK
D
RST
INDUSTRIAL TEMPERATURE RANGE
Q
SIB
7 bit Debounce
Counter
D
E
Q
SIA