EMC2300-AZC-TR SMSC, EMC2300-AZC-TR Datasheet - Page 67

• Manufacturer Part Number: EMC2300-AZC-TR
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC2300-AZC-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
.
SMSC EMC2300
8.2.20
Register
Address
BIT
AVG2
0
1
2
3
4
5
6
7
7Ch
0
0
0
1
MONMD
SFTR[7:5]
NAME
INTEN
Read/
SMSC
SMSC
LPMD
Write
AVG0
AVG1
AVG2
R/W
AVG1
Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL
are not included in the test tree.
Register 7Ch: Special Function Register
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
This register contains the following bits:
X
0
0
1
PWM2, PWM3
Special Function
Register Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AVG0
X
X
0
1
DEFAULT
Table 8.37 Register 7Ch: Special Function Register
REM DIODE 1
0
0
0
0
0
0
1
0
Table 8.38 Special Function Register
(MSb)
AVG2
Bit 7
128
Table 8.39 AVG[2:0] Bit Decoder
16
16
32
Low Power Mode Select.
Monitoring Mode Select.
Global Interrupt enable. When set enables the INT# pin output function.
SMSC - writing this bit may have undesired affects.
SMSC - writing this bit may have undesired affects.
The AVG[2:0] bits determine the amount of averaging for each of the six
measurements that are performed by the hardware monitor before the
reading registers are updated
AVG[2:0] bits are priority encoded where the most significant bit has
highest priority. For example, when the AVG2 bit is asserted, 32 averages
will be performed for each measurement before the reading registers are
updated regardless of the state of the AVG[1:0] bits.
Note:
‘0’ = Sleep Mode
‘1’ = Low Power Mode
‘0’ = Continuous Mode
‘1’ = Cycle Mode
AVG1
Bit 6
DATASHEET
The default for the AVG[2:0] bits is ‘010’b
AVG0
Bit 5
REM DIODE 2
67
128
16
16
32
AVERAGES PER READING
SMSC
Bit 4
DESCRIPTION
INTERNAL DIODE
SMSC
(Table 8.39, "AVG[2:0] Bit
Bit 3
16
32
8
1
INTEN
Bit 2
MONMD
Bit 1
Revision 0.32 (06-23-08)
(VCCP, AND VCC)
ALL VOLTAGE
READINGS
Decoder"). The
LPMD
(LSb)
Bit 0
16
32
8
1
Default
Value
40h