ADV601JS12 Analog Devices Inc, ADV601JS12 Datasheet - Page 12

• Manufacturer Part Number: ADV601JS12
• Description: IC CODEC VIDEO DSP/SRL 160-MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV601JS12

• Rohs Status: RoHS non-compliant
• Data Interface: DSP, Serial
• Resolution (bits): 10 b
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

ADV601
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[15:14] Reserved (always write zero)
FIFO Control Register
Indirect (Read/Write) Register Index 0x01
This register holds the service-request settings for the ADV601’s host interface FIFO, causing interrupts for the “nearly full” and
“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by
32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV601
uses these setting to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).
[3:0]
[15:8]
[7:4]
Video Interface Master/Slave Mode Select, M/S. This bit selects the following:
0
1
Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:
0
1
Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:
0
1
Video Interface Square Pixel Mode Enable, SPE. This bit selects the following:
0
1
Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:
0
1
External DSP Select for bin width calculations, DSP. This bit selects the following:
0
1
Video Interface Software Reset, SWR. This bit has the following effects on ADV601 operations:
0
1
HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV601 operations:
0
1
HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV601 operations:
0
1
Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condi-
tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is
512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
ESL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI during encode)
0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)
1000 FIFO is 1/2 full, reset value
1111 FIFO has only 32 positions empty (480 positions filled)
Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a
condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO
is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
DSL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI)
0001 FIFO has only 32 positions filled (480 positions empty)
1000 FIFO is 1/2 empty, reset value
1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)
Reserved (always write zero)
Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value
Master mode video interface (ADV601 controls video timing, HSYNC-VSYNC are outputs)
525 mode video interface, reset value
625 mode video interface
Decode mode video interface (compressed-to-raw)
Encode mode video interface (raw-to-compressed), reset value
Disable Square Pixel mode video interface
Enable Square Pixel mode video interface, reset value
Bipolar color component mode video interface, reset value
Unipolar color component mode video interface
Host provides bin width calculation, reset value
External DSP provides bin width calculation
Normal operation
Software Reset. This bit is set on hardware reset and must be cleared before the ADV601 can begin processing. (reset value)
When this bit is set during encode, the ADV601 completes processing the current field then suspends operation until the
SWR bit is cleared. When this bit is set during decode, the ADV601 suspends operation immediately and does not resume
operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed.
HSYNC is HI during blanking, reset value
HSYNC is LO during blanking (HI during active)
HIRQ is active LO, reset value
HIRQ is active HI
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