ADV601JS12 Analog Devices Inc, ADV601JS12 Datasheet - Page 16

• Manufacturer Part Number: ADV601JS12
• Description: IC CODEC VIDEO DSP/SRL 160-MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV601JS12

• Rohs Status: RoHS non-compliant
• Data Interface: DSP, Serial
• Resolution (bits): 10 b
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

ADV601
Clock Pins
Name
VCLK/XTAL
VCLKO
Video Interface Pins
Name
VSYNC
HSYNC
FIELD
ENC
VDATA[19:0]
CREF
Pins
2
1
Pins
1
1
1
1
20
1
I
O
I or O
I or O
I or O
O
I/O
I/O
I/O
I/O
PIN FUNCTION DESCRIPTIONS
Description
A single clock (VCLK) or crystal input (across VCLK and XTAL). Acceptable 50%
duty cycle clock signals are as follows:
• 24.54 MHz (Square Pixel NTSC)
• 27 MHz (CCIR601 NTSC/PAL)
• 29.5 MHz (Square Pixel PAL)
If using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. If
using a clock input, use a TTL level input, 50% duty cycle clock with 1 ns (or less)
jitter (measured rising edge to rising edge). Slowly varying, low jitter clocks are
acceptable; up to 5% frequency variation in 0.5 sec.
VCLK Output or VCLK Output divided by two. Select function using Mode
Control register.
Description
Vertical Sync or Vertical Blank. This pin can be either an output (Master Mode) or
an input (Slave Mode). The pin operates as follows:
• Output (Master) HI during inactive lines of video and LO otherwise
• Input (Slave) a HI on this input indicates inactive lines of video
Horizontal Sync or Horizontal Blank. This pin can be either an output (Master
Mode) or an input (Slave Mode). The pin operates as follows:
• Output (Master) HI during inactive portion of video line and LO otherwise
• Input (Slave) a HI on this input indicates inactive portion of video line
Note that the polarity of this signal is modified using the Mode Control register. For
detailed timing information, see the Video Interface section.
Field # or Frame Sync. This pin can be either an output (Master Mode) or an input
(Slave Mode). The pin operates as follows:
• Output (Master) HI during Field1 lines of video and LO otherwise
• Input (Slave) a HI on this input indicates Field1 lines of video
Encode or Decode. This output pin indicates the coding mode of the ADV601 and
operates as follows:
• LO Decode Mode (Video Interface is output)
• HI Encode Mode (Video Interface is input)
Note that this pin can be used to control bus enable pins for devices connected to
the ADV601 Video Interface.
4:2:2 Video Data (8-, 10-, or 12-bit digital component video data). These pins are
inputs during encode mode and outputs during decode mode. When outputs (de-
code) these pins are compatible with 50 pF loads (rather than 30 pF as all other
busses) to meet the high performance and large number of typical loads on this bus.
The performance of these pins varies with the Video Interface Mode set in the
Mode Control register, see the Video Interface section of this data sheet for pin
assignments in each mode.
Note that the Mode Control register also sets whether the color component is
treated as either signed or unsigned.
Clock Reference pin for Philips Interface (VCLK qualifier)—This pin can be either
an output (Master Mode) or an input (Slave Mode). The pin operates as follows:
• Output (Master) HI to qualify VCLK during VCLK phases containing valid de-
• Input (Slave) a HI on this input qualifies VCLK during VCLK phases containing
multiplexed digital video and LO otherwise
valid de-multiplexed digital video.
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