ADV601JS12 Analog Devices Inc, ADV601JS12 Datasheet - Page 38

• Manufacturer Part Number: ADV601JS12
• Description: IC CODEC VIDEO DSP/SRL 160-MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV601JS12

• Rohs Status: RoHS non-compliant
• Data Interface: DSP, Serial
• Resolution (bits): 10 b
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

ADV601
CCIR-656 Video Format Timing
The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video
mode. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for CCIR-656 video, the label CTRL
indicates the VSYNC, HSYNC, and FIELD pins. Also note that for CCIR-656 video mode, the CREF pin is unused.
Parameter
t
t
t
t
Parameter
t
t
t
t
VDATA_DC_D
VDATA_DC_OH
CTRL_DC_D
CTRL_DC_OH
VDATA_EC_S
VDATA_EC_H
CTRL_EC_D
CTRL_EC_OH
(VCLK2 = 0)
(VCLK2 = 1)
(O) VCLKO
(O) VDATA
(I) VDATA
(O) VCLKO
(O) CTRL
(O) CTRL
(I) VCLKO
(I) VCLK
(I) VCLK
NOTE:
USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS.
DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE.
t
VDATA_DC_OH
t
Table XXIII. CCIR-656 Video—Decode Pixel (YCrCb) Timing Parameters
CTRL_DC_OH
VALID
VALID
Table XXIV. CCIR-656 Video—Encode Pixel (YCrCb) Timing Parameters
Description
VDATA Signals, Decode CCIR656 Mode, Delay
VDATA Signals, Decode CCIR656 Mode, Output Hold
CTRL Signals, Decode CCIR656 Mode, Delay
CTRL Signals, Decode CCIR656 Mode, Output Hold
Description
VDATA Bus, Encode CCIR656 Mode, Setup
VDATA Bus, Encode CCIR656 Mode, Hold
CTRL Signals, Encode CCIR656 Mode, Delay
CTRL Signals, Encode CCIR656 Mode, Output Hold
Figure 25. CCIR-656 Video—Decode Pixel (YCrCb) Transfer Timing
Figure 26. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing
ASSERTED
t
CTRL_EC_OH
t
VDATA_DC_D
t
VALID
CTRL_DC_D
t
t
VCLKO_D0
VCLKO_D1
Figure 24. Video Clock Timing
t
CTRL_EC_D
t
VCLK_CYC
–38–
VALID
VALID
t
VDATA_EC_S
ASSERTED
VALID
t
VDATA_EC_H
Min
N/A
2
N/A
3
Min
2
5
N/A
20
VALID
VALID
Max
14
N/A
11
N/A
Max
N/A
N/A
33
N/A
REV. 0
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns