LAN9210-ABZJ SMSC, LAN9210-ABZJ Datasheet - Page 111
LAN9210-ABZJ
Manufacturer Part Number
LAN9210-ABZJ
Description
IC ETHERNET CTLR SGL CHIP 56-QFN
Manufacturer
SMSC
Datasheet
1.LAN9210-ABZJ.pdf
(147 pages)
Specifications of LAN9210-ABZJ
Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
638-1048-6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9210-ABZJ
Manufacturer:
Standard
Quantity:
2 500
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Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
5.4.6
5.4.7
31-16
15-11
31-16
BITS
BITS
10-6
15-0
5-2
1
0
Reserved
PHY Address: For every access to this register, this field must be set to 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9210 to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
Reserved
MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to
be written to the PHY before an MII write operation.
MII_ACC—MII Access Register
This register is used to control the Management cycles to the PHY.
MII_DATA—MII Data Register
This register contains either the data to be written to the PHY register specified in the MII Access
Register, or the read data from the PHY register whose index is specified in the MII Access Register.
Offset:
Default Value:
Offset:
Default Value:
6
00000000h
7
00000000h
DATASHEET
111
DESCRIPTION
DESCRIPTION
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W
32 bits
Revision 2.7 (03-15-10)
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