LAN9210-ABZJ SMSC, LAN9210-ABZJ Datasheet - Page 115

• Manufacturer Part Number: LAN9210-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC

Specifications of LAN9210-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1048-6

Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
5.4.13
31-17
BITS
15-2
16
1
0
Reserved
TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE.
This bit may only be changed if the TX data path is disabled.
0: The TXCOE is bypassed
1: The TXCOE is enabled
Reserved
RX Checksum Offload Engine Mode (RXCOE_MODE) This register indicates whether the RXCOE
will check for VLAN tags or a SNAP header prior to beginning its checksum calculation. In its default
mode, the calculation will always begin 14 bytes into the frame.
The RXCOE_MODE may only be changed if the ESS RX path is disabled.
0: Begin checksum calculation after first 14 bytes of Ethernet Frame
1: Begin checksum calculation at start of L3 packet by adjusting for VLAN tags and/or SNAP header.
RX Checksum Offload Engine Enable (RXCOE_EN). This bit enables/disables the Receive COE.
This bit may only be changed if the RX data path is disabled.
0: The RXCOE is bypassed
1: The RXCOE is enabled
Note:
COE_CR—Checksum Offload Engine Control Register
This register controls the transmit and receive checksum offload engines.
Offset:
Default Value:
When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of
the
simultaneously.
MAC_CR—MAC Control
D
00000000h
DATASHEET
Register) and vice versa. These functions cannot be enabled
115
DESCRIPTION
Attribute:
Size:
R/W
32 bits
Revision 2.7 (03-15-10)