LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 158

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical
Note 3: The Activate Register for Logical Device 5 (Serial Port 2) is reset by VTR POR only.
Note 4: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 5: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for
SMSC LPC47B27x
LOGICAL
NUMBER
DEVICE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing
one sets or clears the other.
Device I/O map, then read or write is not valid and is ignored.
logical device 3 and 5 is 0x04.
Serial Port 1
Serial Port 2
LOGICAL
Reserved
Reserved
Reserved
DEVICE
Parallel
FDC
Table 65 - I/O Base Address Configuration Register Description
Port
REGISTER
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
0x62,0x63
INDEX
n/a
n/a
n/a
DATASHEET
the base address is on an 8-
ON 8 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
EPP is only available when
(all modes supported,
(EPP Not supported)
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[0x0100:0x0FFC]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
byte boundary)
BASE I/O
(NOTE 1)
RANGE
n/a
n/a
n/a
or
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TDR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
n/a
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h :
cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : CIrCC SCE Registers
+1 : CIrCC SCE Registers
+2 : CIrCC SCE Registers
+3 : CIrCC SCE Registers
+4 : CirCC SCE Registers
+5 : CirCC SCE Registers
+6 : CirCC SCE Registers
+7 : CIrCC SCE Registers
n/a
BASE OFFSETS
FIXED
Rev. 04-17-07