LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 66
LPC47B272-MS
Manufacturer Part Number
LPC47B272-MS
Description
IC CTRLR SUPER I/O LPC 100-QFP
Manufacturer
SMSC
Datasheet
1.LPC47B272-MS.pdf
(195 pages)
Specifications of LPC47B272-MS
Controller Type
I/O Controller
Interface
LPC
Voltage - Supply
3.3V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1019
Available stocks
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Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
SMSC LPC47B27x
DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
When operating in the XT mode, this bit will be set any time that the transmitter shift register
is empty.
This bit no longer has a pin associated with it.
When operating in the XT mode, this register is not available.
These bits are always zero in the non-FIFO mode.
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register
(runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register
at offset 0x21).
DATASHEET
- 66 -
Rev. 04-17-07
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