FDC37B787-NS SMSC, FDC37B787-NS Datasheet - Page 159
FDC37B787-NS
Manufacturer Part Number
FDC37B787-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet
1.FDC37B787-NS.pdf
(249 pages)
Specifications of FDC37B787-NS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
70mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1006
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PME Enable Register (PME_EN)
Register Location: <PM1_BLK>+11h System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
PME Status Register 1 (PME_STS 1)
Register Location: <PM1_BLK>+Ch System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
PME Status Register 2 (PME_STS2)
Register Location: <PM1_BLK>+Dh System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
PME Enable Register 1 (PME_EN1)
Register Location: <PM1_BLK>+Eh System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
•
•
•
•
•
•
•
•
DEVINT
_STS
The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it (if there are
no pending PME events) and cause the FDC37C78X to stop asserting the nPME, if enabled. See
Figure 5.
Writing a “0” has no effect on the PME_Status bit.
The PME_Status bit is reset to “0” during VBAT Power-On-Reset.
Setting the PME_En bit to “1” enables the FDC37B78x to assert the nPME signal.
When the PME_En bit is reset to “0”, nPME signal assertion is disabled.
The PME_En bit is reset to “0” during VBAT Power-On-Reset.
The PME Status registers indicate the state of the individual FDC37B78x PME wake sources,
independent of the state of the individual source enables or the PME_En bit.
If the wake source has asserted a wake event, the associated PME Status bit will be “1”. The wake
source bits in the PME Status registers are read/write-clear: an active (“1”) PME Status bit can only
be cleared by writing a “1” to the bit. Writing a “0” to bits in the PME Wake Status register has no
effect.
D7
D7
GP17
D7
RTC_PME
_STS
D6
D6
GP16
D6
D5
nRING
GP15
D5
D5
RESERVED
D4
GP14
D4
MOUSE
D4
D3
GP13
D3
161
KBD
D3
D2
GP12
D2
RI1
D2
GP11
D1
D1
RI2
D1
GP10
PME_En
D0
D0
CIR
D0
DEFAUL
0x00
T
DEFAULT
DEFAULT
0x00
0x00
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