FDC37B787-NS SMSC, FDC37B787-NS Datasheet - Page 224
FDC37B787-NS
Manufacturer Part Number
FDC37B787-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet
1.FDC37B787-NS.pdf
(249 pages)
Specifications of FDC37B787-NS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
70mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1006
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CLOCK TIMING
Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while
CLOCKI
RESET_DRV
NAME
NAME
t1
t2
t1
t2
t4
the clock is running and stable.
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
RESET width (Note 1)
DESCRIPTION
FIGURE 16 - INPUT CLOCK TIMING
TABLE 95 - INPUT CLOCK TIMING
DESCRIPTION
FIGURE 17 - RESET TIMING
TABLE 96 - RESET TIMING
232
t4
t2
MIN
MIN
1.5
31.25
16.53
TYP
70
35
TYP
t2
MAX
MAX
5
UNITS
UNITS
μs
ns
ns
μs
μs
ns
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