FDC37B787-NS SMSC, FDC37B787-NS Datasheet - Page 206
FDC37B787-NS
Manufacturer Part Number
FDC37B787-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet
1.FDC37B787-NS.pdf
(249 pages)
Specifications of FDC37B787-NS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
70mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1006
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Default = 0x00
on Vcc POR or
Reset_Drv
WDT_VAL
Default = 0x00
on Vcc POR or
Reset_Drv
WDT_CFG
Default = 0x00
on Vcc POR or
Reset_Drv
WDT_CTRL
Default = 0x00
Cleared by VTR
POR
NAME
REG INDEX
0xF2
0xF3
0xF4
Note: if the logical device's activate bit is not set then
bits 0 and 1 have no effect.
Watch-dog Timer Time-out Value
Binary coded, units = minutes(default) or seconds,
selectable via Bit[7] of Reg 0xF1, LD 8.
0x00 Time out disabled
0x01 Time-out = 1 minute/second
.........
0xFF Time-out = 255 minutes/seconds
Watch-dog timer Configuration
Bit[0] Joy-stick Enable
=1 WDT is reset upon an I/O read or write of the
Game Port
=0 WDT is not affected by I/O reads or writes to the
Game Port.
Bit[1] Keyboard Enable
=1 WDT is reset upon a Keyboard interrupt.
=0 WDT is not affected by Keyboard interrupts.
Bit[2] Mouse Enable
=1 WDT is reset upon a Mouse interrupt
=0 WDT is not affected by Mouse interrupts.
Bit[3] PWRLED Time-out enable
=1 Enables the Power LED to toggle at a 1Hz rate with
50 percent duty cycle while the Watch-dog Status bit
is set.
=0 Disables the Power LED toggle during Watch-dog
timeout status.
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
.........
0011 = IRQ3
0010 = Invalid
0001 = IRQ1
0000 = Disable
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1 WD timeout occured
=0 WD timer counting
Bit[1] Power LED Toggle Enable, R/W
=1 Toggle Power LED at 1Hz rate with 50 percent duty
cycle. (1/2 sec. on, 1/2 sec. off)
=0 Disable Power LED Toggle
Bit[2] Force Timeout, W
=1 Forces WD timeout event; this bit is self-clearing
Bit[3] P20 Force Timeout Enable, R/W
= 0 Minutes (default)
= 1 Seconds
209
DEFINITION
STATE
C
C
C
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