ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 10

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC28J60
APPENDIX A:
Rev A Document (10/2007)
Original revision. Silicon errata issues 1 (Reset),
2 (Oscillator – CLKOUT Pin), 3 (Memory – Ethernet
Buffer), 4 (Interrupts), 5-8 (PHY), 9 (PHY LEDs),
10 (Transmit Logic), 11 (Memory – Ethernet Buffer),
12 (Transmit Logic), 13-14 (PHY) and 15 (DMA).
Rev B Document (07/2008)
Updated the revision of the referenced data sheet.
Changed the revision identifier for this device as the
previous version contained an error.
Rev C Document (07/2010)
Revises the document to include all released silicon
revisions of the device, starting with revision B1, and
removes “silicon revision B7” from the title. Order of
issues has been re-aligned to better reflect sequential
issue history:
• 1 (MAC Interface)
• 2 (Reset)
• 3 (Core)
• 4 (Oscillator)
• 5 (Memory)
• 6 (Interrupts)
• 7-10 (PHY)
• 11 (PHY LEDs)
• 12 (Transmit Logic)
• 13 (PHY)
• 14 (Memory – Ethernet Buffer)
• 15 (Transmit Logic)
• 16 (PHY)
• 17 (DMA)
Adds new silicon issues 18 (Receive Filter) and
19 (SPI Interface) to all silicon revisions.
Makes minor clarifying changes and typographic
corrections to issues 2, 3, 4, 5, 7, 13 and 14.
Revises issue 8 (PHY) to reflect that the current
revision of the data sheet correctly describes the
current silicon revision.
Adds
Pattern), 2 (Exiting Link Test Fail State) and 3 (Collision
Handling) from previous revisions B1 and B4.
Adds Data Sheet Clarification 1 (Receive Filters).
This document replaces these errata documents:
• DS80254, “ENC28J60 Revision B1 Silicon Errata”
• DS80257, “ENC28J60 Revision B4 Silicon Errata”
• DS80264, “ENC28J60 Revision B5 Silicon Errata”
DS80349C-page 10
Ethernet
Conformance
DOCUMENT
REVISION HISTORY
Issues
1 (TP_IDL
 2010 Microchip Technology Inc.