UJA1075TW/5V0/WD,1 NXP Semiconductors, UJA1075TW/5V0/WD,1 Datasheet - Page 24

• Manufacturer Part Number: UJA1075TW/5V0/WD,1
• Description: IC SBC CAN/LIN HS 5V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1075TW/5V0/WD,1

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 83µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1075_2
Product data sheet
6.7.3.1 TXDC dominant time-out function
6.7.3.2 Pull-up on TXDC pin
6.7.2 Split circuit
6.7.3 Fail-safe features
6.8 LIN transceiver
Pin SPLIT provides a DC stabilized voltage of 0.5V
only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V
used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the
center tap of the split termination (see
A transceiver in the network that is not supplied and that generates a significant leakage
current from the bus lines to ground, can result in a recessive bus voltage of < 0.5V
this event, the split circuit will stabilize the recessive voltage at 0.5V
transmission will not generate a step in the common-mode signal which would lead to
poor ElectroMagnetic Emission (EME) performance.
A TXDC dominant time-out timer is started when pin TXDC is forced LOW. If the LOW
state on pin TXDC persists for longer than the TXDC dominant time-out time (t
the transmitter will be disabled, releasing the bus lines to recessive state. This function
prevents a hardware and/or software application failure from driving the bus lines to a
permanent dominant state (blocking all network communications). The TXDC dominant
time-out timer is reset when pin TXDC goes HIGH. The TXDC dominant time-out time
also defines the minimum possible bit rate of 10 kbit/s.
Pin TXDC has an internal pull-up towards V
pin is left floating.
The analog sections of the UJA1075 LIN transceiver is identical to that integrated into the
TJA1021.
The transceiver is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates
from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
Fig 10. Stabilization circuitry and application using the SPLIT pin
All information provided in this document is subject to legal disclaimers.
V
in normal mode;
otherwise floating
SPLIT
Rev. 02 — 27 May 2010
= 0.5 V
CC
Figure
R
R
V2
GND
UJA1075
High-speed CAN/LIN core system basis chip
V1
10).
to ensure a safe defined state in case the
SPLIT
CANL
V2
CANH
. It is activated in CAN Active mode
60 Ω
60 Ω
015aaa120
SPLIT
V2
. So a start of
UJA1075
© NXP B.V. 2010. All rights reserved.
circuit can be
to(dom)TXDC
24 of 53
V2
. In
),