UJA1075TW/5V0/WD,1 NXP Semiconductors, UJA1075TW/5V0/WD,1 Datasheet - Page 26

• Manufacturer Part Number: UJA1075TW/5V0/WD,1
• Description: IC SBC CAN/LIN HS 5V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1075TW/5V0/WD,1

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 83µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1075_2
Product data sheet
6.9 Local wake-up input
edge on pin TXDL. If the pin remains LOW for longer than the TXDL dominant time-out
time (t
The timer is reset by a positive edge on the TXDL pin.
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting
bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are
sampled continuously). The sampling will be performed on the rising edge of WBIAS (see
Figure
(WBC) in the Mode_Control register.
Figure 12
Fig 11. Wake-up pin sampling synchronized with WBIAS signal
to(dom)TXDL
11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit
Wake-up int
WAKEx pin
WBIAS pin
shows typical circuit for implementing cyclic sampling of the wake-up inputs.
WBIASI
(internal)
All information provided in this document is subject to legal disclaimers.
), the transmitter is disabled, driving the bus lines to a recessive state.
Rev. 02 — 27 May 2010
enable bias
Table
High-speed CAN/LIN core system basis chip
6). These bits can also be used to disable
disable bias
disable bias
wake level latched
(Table
4).
UJA1075
© NXP B.V. 2010. All rights reserved.
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