DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 20

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS21Q42
Signal Name: BTS
Signal Description: Bus Type Select
Signal Type: Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name: RD*(DS*)
Signal Description: Read Input (Data Strobe)
Signal Type: Input
RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 21 .
Signal Name: FS0 AND FS1
Signal Description: Framer Selects
Signal Type: Input
Selects which of the four framers to be accessed.
Signal Name: CS*
Signal Description: Chip Select
Signal Type: Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name: WR*( R/W*)
Signal Description: Write Input(Read/Write)
Signal Type: Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name: TEST
Signal Description: 3–State Control
Signal Type: Input
Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when
FMS = 0 and JTRST is tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST = 1.
Useful in board level testing.
Signal Name: JTRST
Signal Description: IEEE 1149.1 Test Reset
Signal Type: Input
If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally. If FMS = 0: JTAG
functionality is available and JTRST is pulled up internally by a 10-kilo ohm resistor. If FMS = 0, and
boundary scan is not used this pin should be held low. This signal is used to asynchronously reset the test
access port controller. The device enters the DEVICE ID MODE when JTRST is pulled high. The
device operates as a T1/E1 transceiver if JTRST is pulled low.
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