DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 36

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB)
RJC
RESALGN
TESALGN
SYMBOL
RCM4
RCM3
RCM2
RCM1
RCM0
RJC
RESALGN
POSITION
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
CCR6.1
CCR6.0
TESALGN
NAME AND DESCRIPTION
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Receive Elastic Store Align. Setting this bit from a zero to a one
may force the receive elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if the
pointer separation is already greater or equal to half a frame. If
pointer separation is less then half a frame, the command will be
executed and data will be disrupted. Should be toggled after
RSYSCLK has been applied and is stable. Must be cleared and set
again for a subsequent align. See Section 13 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if the
pointer separation is already greater or equal to half a frame. If
pointer separation is less then half a frame, the command will be
executed and data will be disrupted. Should be toggled after
TSYSCLK has been applied and is stable. Must be cleared and set
again for a subsequent align. See Section 13 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the RDS0M
register. See Section 9 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM4
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RCM3
RCM2
RCM1
(LSB)
RCM0