DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 57

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
20 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
CH8
CH16
CH24
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
CH16
CH24
CH8
SYMBOLS
SYMBOLS
CH1 – 24
CH1 – 24
CLOCK BLOCKING REGISTERS
CH7
CH15
CH23
CH15
CH23
CH7
CH6
CH14
CH22
RCBR1.0 - 3.7
TCBR1.0 - 3.7
CH14
CH22
POSITIONS
POSITIONS
CH6
CH5
CH13
CH21
CH13
CH21
CH5
NAME AND DESCRIPTION
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
NAME AND DESCRIPTION
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
CH4
CH12
CH20
CH12
CH20
CH4
57 of 116
CH3
CH11
CH19
CH11
CH19
CH3
CH2
CH10
CH18
CH10
CH18
CH2
(LSB)
CH1
CH9
CH17
(LSB)
CH17
CH1
CH9
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
The