DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 73

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.4 D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to
1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL
register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the these message fields
via the TFDL and RFDL registers. Please see the separate Application Note for a detailed description of
how to implement a SLC–96
16.
Each framer in the DS21Q42 has the ability to generate and detect a repeating bit pattern that is from one
to eight bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit
Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1
bits in the In–Band Code Control (IBCC) register. Once this is accomplished, the pattern will be
transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the transmit
formatter is programmed to not insert the F–bit position) the framer will overwrite the repeating pattern
once every 193 bits to allow the F–bit position to be sent. See Figure 20-15 for more details. As an
example, if the user wished to transmit the standard “loop up” code for Channel Service Units which is a
repeating pattern of ...10000100001... then 80h would be loaded into TDR and the length would set to 5
bits.
Each framer can detect two separate repeating patterns to allow for both a “loop up” code and a “loop
down” code to be detected. The user will program the codes to be detected in the Receive Up Code
Definition (RUPCD) register and the Receive Down Code Definition (RDNCD) register and the length of
each pattern will be selected via the IBCC register. The framer will detect repeating pattern codes in both
framed and unframed circumstances with bit error rates as high as 10**–2. The code detector has a
nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status
bit (LUP at SR1.7 and LDN at SR1.6) will be set to a one. Normally codes are sent for a period of
5 seconds. it is recommend that the software poll the framer every 100 ms to 1000 ms until 5 seconds has
relapsed to insure that the code is continuously present.
IBCC: IN–BAND CODE CONTROL REGISTER (Address=12 Hex)
(MSB)
TC1
SYMBOL
RDN2
RDN1
RDN0
RUP2
RUP1
RUP0
TC1
TC0
PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION
TC0
POSITION
IBCC.7
IBCC.6
IBCC.5
IBCC.4
IBCC.3
IBCC.2
IBCC.1
IBCC.0
RUP2
NAME AND DESCRIPTION
Transmit Code Length Definition Bit 1. See Table 16–1
Transmit Code Length Definition Bit 0. See Table 16–1
Receive Up Code Length Definition Bit 2. See Table 16–2
Receive Up Code Length Definition Bit 1. See Table 16–2
Receive Up Code Length Definition Bit 0. See Table 16–2
Receive Down Code Length Definition Bit 2. See Table 16–2
Receive Down Code Length Definition Bit 1. See Table 16–2
Receive Down Code Length Definition Bit 0. See Table 16–2
RUP1
73 of 116
RUP0
RDN2
RDN1
(LSB)
RDN0