DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 64

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HSR: HDLC STATUS REGISTER (Address = 01 Hex)
Note: The RBOC, RPE, RPS, and TMEND bits are latched and are cleared when read.
(MSB)
RBOC
SYMBOL
SYMBOL
TMEND
TCRCD
RHALF
THALF
RBOC
TZSD
RNE
RPE
RPS
TNF
RPE
POSITION
POSITION
HCR.1
HCR.0
HSR.7
HSR.6
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
RPS
NAME AND DESCRIPTION
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
NAME AND DESCRIPTION
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to a
No Valid Code seen or vice versa. The setting of this bit prompt
the user to read the RBOC register for details.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as a
CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects an
opening byte. The setting of this bit prompts the user to read the
RHIR register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this bit
prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts
the user to read the THIR register for details.
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this bit
prompts the user to read the THIR register for details.
RHALF
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RNE
THALF
TNF
TMEND
(LSB)