ISP1161A1BD ST-Ericsson Inc, ISP1161A1BD Datasheet - Page 12
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ISP1161A1BD
Manufacturer Part Number
ISP1161A1BD
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1161A1BMGA.pdf
(137 pages)
Specifications of ISP1161A1BD
Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1162
ISP1161A1BD,157
ISP1161A1BD,157
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Philips Semiconductors
7. Functional description
9397 750 13961
Product data
7.1 PLL clock multiplier
7.2 Bit clock recovery
7.3 Analog transceivers
7.4 Philips Serial Interface Engine (SIE)
7.5 SoftConnect
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No
external components are required for the operation of the PLL.
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using a 4 times over-sampling principle. It is able to track jitter and frequency drift as
specified in the Universal Serial Bus Specification Rev. 2.0 .
Three sets of transceivers are embedded in the chip: two are used for downstream
ports with USB connector type A; one is used for upstream port with USB connector
type B. The integrated transceivers are compliant with the Universal Serial Bus
Specification Rev. 2.0 . They interface directly with the USB connectors and cables
through external termination resistors.
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel/serial conversion, bit (de)stuffing, CRC
checking/generation, Packet IDentifier (PID) verification/generation, address
recognition, handshake evaluation/generation. There are separate SIEs in the HC
and the DC.
The connection to the USB is accomplished by bringing D (for full-speed USB
devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161A1 DC, the 1.5 k
pull-up resistor is integrated on-chip and is not connected to V
connection is established through a command sent by the external/system
microcontroller. This allows the system microcontroller to complete its initialization
sequence before deciding to establish connection with the USB. Re-initialization of
the USB connection can also be performed without disconnecting the cable.
The ISP1161A1 DC will check for USB V
established. V
Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 %
tolerance specified by the USB specification. However, the overall voltage
specification for the connection can still be met with a good margin. The decision to
make use of this feature lies with the USB equipment designer.
BUS
Rev. 03 — 23 December 2004
sensing is provided through pin D_VBUS.
USB single-chip host and device controller
BUS
availability before the connection can be
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A1
CC
by default. The
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