ISP1161ABM-S ST-Ericsson Inc, ISP1161ABM-S Datasheet - Page 13

• Manufacturer Part Number: ISP1161ABM-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABM-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
8. Microprocessor bus interface
9397 750 13962
Product data
7.6 GoodLink
8.1 Programmed I/O (PIO) addressing mode
8.2 DMA mode
Indication of a good USB connection is provided at pin GL through GoodLink
technology. During enumeration, the LED indicator will blink on momentarily. When
the DC has been successfully enumerated (the device address is set), the LED
indicator will remain permanently on. Upon each successful packet transfer (with
ACK) to and from the ISP1161A the LED will blink off for 100 ms. During ‘suspend’
state the LED will remain off.
This feature provides a user-friendly indication of the status of the USB device, the
connected hub and the USB traffic. It is a useful field diagnostics tool for isolating
faulty equipment. It can therefore help to reduce field support and hotline overhead.
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1161A appears as a
memory device with a 16-bit data bus and uses only two address lines: A1 and A0 to
access the internal control registers and FIFO buffer RAM. Therefore, the ISP1161A
occupies only four I/O ports or four memory locations of a microprocessor. External
microprocessors can read from or write to the ISP1161A internal control registers and
FIFO buffer RAM through the Programmed I/O (PIO) operating mode.
the Programmed I/O interface between a microprocessor and an ISP1161A.
The ISP1161A also provides DMA mode for external microprocessors to access its
internal FIFO buffer RAM. Data can be transferred by DMA operation between a
microprocessor’s system memory and the ISP1161A internal FIFO buffer RAM.
Remark: The DMA operation must be controlled by the external microprocessor
system DMA controller (Master).
Fig 8. Programmed I/O interface between a microprocessor and an ISP1161A.
Rev. 03 — 23 December 2004
PROCESSOR
MICRO-
Full-speed USB single-chip host and device controller
D [ 15:0 ]
IRQ1
IRQ2
WR
RD
CS
A2
A1
µP bus I/F
D [ 15:0 ]
RD
WR
CS
A1
A0
INT1
INT2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
004aaa086
ISP1161A
Figure 8
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