CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 24

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
Table 11-1. System Status and Control Register (CPU_SCR) [0xFF] [R/W]
11.1
POR occurs every time the power to the device is switched on.
POR is released when the supply is typically 2.6V for the
upward supply transition, with typically 50 mV of hysteresis
during the power-on transient. Bit 4 of the System Status and
Control Register (CPU_SCR) is set to record this event (the
register contents are set to 00010000 by the POR). After a
POR, the microprocessor is held off for approximately 20 ms
for the V
instruction at address 0x00 in the Flash. If the V
drops below the POR downward supply trip point, POR is
reasserted. The V
4V in 0 to 200 ms.
Important: The PORS status bit is set at POR and can only
be cleared by the user. It cannot be set by firmware.
11.2
The user has the option to enable the WDT. The WDT is
enabled by clearing the PORS bit. Once the PORS bit is
Note:
The bits of the CPU_SCR register are used to convey status and control of events for various functions of an enCoRe II device
Bit 7: GIES
The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit, which
was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now readable. When
this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor will
service interrupts
0 = Global interrupts disabled
1 = Global interrupt enabled
Bit 6: Reserved
Bit 5: WDRS
The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine the type of
reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
Bit 4: PORS
The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the type of
reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared)
Bit 3: SLEEP
Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending. The Sleep bit is covered
in more detail in the Sleep Mode section
0 = Normal operation
1 = Sleep
Bit [2:1]: Reserved
Bit 0: STOP
This bit is set by the user to halt the CPU. The CPU will remain halted until a reset (WDR, POR, or external reset) has taken
place. If an application wants to stop code execution until a reset, the preferred method would be to use the HALT instruction
rather than writing to this bit
0 = Normal CPU operation
1 = CPU is halted (not recommended)
4.
Read/Write
Default
C = Clear. This bit can only be cleared by the user and cannot be set by firmware.
Field
Bit #
Power-on Reset
Watchdog Timer Reset
CC
supply to stabilize before executing the first
CC
GIES
R
7
0
supply needs to ramp linearly from 0 to
Reserved
6
–
0
WDRS
R/C
5
0
[4]
CC
voltage
PORS
R/C
4
1
[4]
cleared, the WDT cannot be disabled. The only exception to
this is if a POR event takes place, which will disable the WDT.
The sleep timer is used to generate the sleep time period and
the Watchdog time period. The sleep timer uses the Internal
32-KHz Low-power Oscillator system clock to produce the
sleep time period. The user can program the sleep time period
using the Sleep Timer bits of the OSC_CR0 Register
(Table 10-5). When the sleep time elapses (sleep timer
overflows), an interrupt to the Sleep Timer Interrupt Vector will
be generated.
The Watchdog Timer period is automatically set to be three
counts of the Sleep Timer overflows. This represents between
two and three sleep intervals depending on the count in the
Sleep Timer at the previous WDT clear. When this timer
reaches three, a WDR is generated.
The user can either clear the WDT, or the WDT and the Sleep
Timer. Whenever the user writes to the Reset WDT Register
(RES_WDT), the WDT will be cleared. If the data that is written
is the hex value 0x38, the Sleep Timer will also be cleared at
the same time.
Sleep
R/W
3
0
2
–
0
Reserved
1
–
0
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Stop
R/W
0
0