CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 42

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
17.2
The sequence of events that occur during interrupt processing
is as follows:
1. An interrupt becomes active, either because:
2. The current executing instruction finishes.
3. The internal interrupt is dispatched, taking 13 cycles. During
4. Program execution vectors to the interrupt table. Typically,
5. The ISR executes. Note that interrupts are disabled since
this time, the following actions occur: he MSB and LSB of
Program Counter and Flag registers (CPU_PC and
CPU_F) are stored onto the program stack by an automatic
CALL instruction (13 cycles) generated during the interrupt
acknowledge process.
a LJMP instruction in the interrupt table sends execution to
the user’s Interrupt Service Routine (ISR) for this interrupt
GIE = 0. In the ISR, interrupts can be re-enabled if desired
a. The interrupt condition occurs (e.g., a timer expires)
b. A previously posted interrupt is enabled through an up-
a. The PCH, PCL, and Flag register (CPU_F) are stored
b. The CPU_F register is then cleared. Since this clears the
d. The interrupt vector is read from the interrupt controller
c. An interrupt is pending and GIE is set from 0 to 1 in the
c. The PCH (PC[15:8]) is cleared to zero
date of an interrupt mask register
CPU Flag register.
onto the program stack (in that order) by an automatic
CALL instruction (13 cycles) generated during the inter-
rupt acknowledge process
GIE bit to 0, additional interrupts are temporarily dis-
abled
and its value placed into PCL (PC[7:0]). This sets the
program counter to point to the appropriate address in
the interrupt table (e.g., 0004h for the POR/LVD inter-
rupt)
GPIO, etc.)
Interrupt
Source
(Timer,
Interrupt Processing
1
INT_CLRx Write
Interrupt Taken
D
or
R
Q
Figure 17-1. Interrupt Controller Block Diagram
Mask Bit Setting
Interrupt
INT_MSKx
Posted
Interrupt
Pending
17.3
The time between the assertion of an enabled interrupt and the
start of its ISR can be calculated from the following equation.
Latency = Time for current instruction to finish + Time for
internal interrupt routine to execute + Time for LJMP
instruction in interrupt table to execute.
For example, if the 5-cycle JMP instruction is executing when
an interrupt becomes active, the total number of CPU clock
cycles before the ISR begins would be as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt
routine) + (7 cycles for LJMP) = 21 to 25 cycles.
In the example above, at 24 MHz, 25 clock cycles take 1.042
ms.
17.4
17.4.1
The Interrupt Clear Registers (INT_CLRx) are used to enable
the individual interrupt sources’ ability to clear posted inter-
rupts.
When an INT_CLRx register is read, any bits that are set
indicates an interrupt has been posted for that hardware
resource. Therefore, reading these registers gives the user the
ability to determine all posted interrupts.
6. The ISR ends with a RETI instruction which restores the
7. Execution resumes at the next instruction, after the one that
by setting GIE = 1 (care must be taken to avoid stack
overflow).
Program Counter and Flag registers (CPU_PC and
CPU_F). The restored Flag register re-enables interrupts,
since GIE = 1 again.
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts will be
processed before the next normal program instruction.
Encoder
Priority
Interrupt Latency
Interrupt Registers
Interrupt Clear Register
CPU_F[0]
Interrupt Vector
GIE
Interrupt
Request
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