CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 55

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
24.0
Note: In the R/W column,
b = Both Read and Write
r = Read Only
w = Write Only
c = Read/Clear
? = Unknown
d = calibration value. Should not change during normal use
50–57
58–5F
60–67
Addr
1EB
1E0
1E3
1E4
DA
DB
DC
DE
DF
3C
3D
E0
E1
E2
E3
FF
39
40
41
42
43
44
45
46
73
74
--
--
--
--
--
-
Register Summary
OSCLCKCR
EP0MODE
EP1MODE
EP2MODE
INT_MSK3
INT_MSK2
INT_MSK1
INT_MSK0
CPU_PCH
CPU_SCR
INT_CLR0
INT_CLR1
INT_CLR2
CPU_PCL
OSC_CR0
EP0DATA
EP1DATA
EP2DATA
VREGCR
RESWDT
SPIDATA
USBXCR
EP0CNT
EP1CNT
EP2CNT
CPU_SP
ECO_TR
VLTCMP
INT_VC
USBCR
CPU_A
CPU_X
CPU_F
LVDCR
SPICR
Name
GPIO Port
ENSWINT
GPIO Port
Sleep Duty Cycle [1:0]
up Enable
Int Enable
Int Enable
USB Pull-
Reserved GPIO Port
Reserved GPIO Port
TCAP0
TCAP0
Enable
Toggle
Toggle
Toggle
Swap
Setup
GIES
USB
Data
Data
Data
rcv’d
Stall
Stall
7
1
1
Reserved
Reserved
Data Valid
Data Valid
Data Valid
Int Enable
Int Enable
Int Enable
Reserved
Reserved
Reserved
Reserved
LSB First
IN rcv’d
Interval
Interval
Sleep
Sleep
Timer
Timer
Timer
Timer
Prog
Prog
6
4
4
(continued)
GPIO Port
GPIO Port
OUT rcv’d ACK’d trans
Int Enable
Int Enable
Int Enable
No Buzz
NAK Int
NAK Int
Enable
Enable
WDRS
Timer
Timer
INT1
1-ms
1-ms
INT1
5
3
3
PORLEV[1:0]
Comm Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO Port 2 PS/2 Data
GPIO Port 2
GPIO Port 0
Ack’d trans
Ack’d trans
USB Active USB Reset
USB Active
Reset Watchdog Timer [7:0]
Temporary Register T1 [7:0]
Endpoint 0 Data Buffer [7:0]
Endpoint 1 Data Buffer [7:0]
Endpoint 2 Data Buffer [7:0]
GPIO Port
Int Enable
Int Enable
Int Enable
Program Counter [15:8]
PORS
Pending Interrupt [7:0]
Program Counter [7:0]
Sleep Timer [1:0]
XOI
4
0
Stack Pointer [7:0]
SPIData[7:0]
Reserved
Device Address[6:0]
X[7:0]
USB Reset
PS/2 Data
Int Enable
Int Enable
Reserved
Receive
Receive
Low Int
Reserved
Enable
CPOL
Super
Sleep
Low
SPI
SPI
3
Reserved
SPI Transmit
SPI Transmit
Int Enable
Int Enable
Int Enable
USB EP2
USB EP2
Reserved
CPHA
Carry
INT2
INT2
Byte Count[3:0]
Byte Count[3:0]
Byte Count[3:0]
2
Mode[3:0]
Mode[3:0]
Mode[3:0]
CPU Speed [2:0]
Keep Alive
Fine Tune
Int Enable
Int Enable
Int Enable
Reserved
VM[2:0]
USB EP1
USB EP1
Counter
Counter
16-bit
16-bit
Wrap
Wrap
INT0
INT0
Only
Zero
LVD
1
SCLK Select
USB Force
Int Enable
Int Enable
POR/ LVD
Int Enable
POR/LVD
USB EP0
USB EP0
Global IE
Osclock
Disable
Enable
TCAP1
TCAP1
VREG
PPOR
State
USB
Stop
0
wwwwwwww
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
ccccbbbb
-bbbbbbb
-bbbbbbb
--bb-bbbb
b-bcbbbb
b-bcbbbb
---brwww
--bbbbbb
r-ccb--b
------bb
------bb
b------b
bb------
b-------
--------
--------
--------
--------
--------
------rr
R/W
CY7C63310
CY7C638xx
CY7C639xx
Page 55 of 68
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