CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 68

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
Document History Page
Document Title: CY7C63310/CY7C638xx/CY7C639xx enCoRe II Low-Speed USB Peripheral Controller
Document Number: 38-08035
Rev.
*A
*B
*C
*D
*E
**
ECN No.
131323
221881
271232
299179
322053
341277
Issue Date
See ECN
See ECN
See ECN
See ECN
See ECN
12/11/03
Change
Orig. of
XGR
BON
BON
BON
KKU
BHA
TVR
New data sheet
information to preliminary
Reformatted
Updated with the latest information
Corrected 24-PDIP pinout typo in Table 5.1 Added Table 10-1.
Updated Table 9-5, Table 10-4, Table 13-1, Table 17-2, Table 17-4, Table 17-6.
Section 5: Removed the VREG from the CY7C63310 and CY7C63801.
Removed SCLK and SDATA. Created a separate pinout diagram for the
CY7C63813.
Added the GPIO Block Diagram (Figure 14-1.)
Table 10-5: Changed the Sleep Timer Clock unit from 32 KHz count to Hz
Table 21-1: Added more descriptions to the register
Corrected V
Updated V
Added footnote to pin description table for D+/D- pins.
Added Typical Values to Low Voltage Detect table.
Corrected Pin label on 16-pin PDIP package.
Corrected minor typos
Added Register descriptions and package information, changed from advance
and Table 15-2. Added various updates to the GPIO Section (Section 14.0).
Corrected Table 15-3. Corrected Figure 27-6 and Figure 27-7. Added the 16-pin
PDIP package diagram (Section 29.0).
Introduction section: Last para removed Low-voltage reset. There is no LVR
there is only LVD (Low voltage detect). explained more about LVD and POR.
Changed capture pins from P0.0,P0.1 to P0.5,P0.6.
Table 6-1: Changed table heading (Removed Mnemonics and made as Register
names). Table 9-5: Included #of rows for different flash sizes
Section10-1: Changed CPUCLK selectable options from n=0-5,7,8 to n=0-5,7.
Clocks section: Changed ITMRCLK division to 1,2,3,4. updated the sources to
ITMRCLK, TCAPCLKs. Mentioned P17 is TTL enabled permanently. Corrected
FRT, PIT data write order. Updated INTCLR,INTMSK registers. in the register
table also. DC spec sheet: changed LVR to LVD included max min program-
mable trip points based on char data. Updated the 50ma sink pins on 638xx,
639xx. Keep-alive voltage mentioned corresponding to Keep-alive current of
20uA. Included Notes regarding VOL,VOH on P1.0,P1.1 and TMDO spec. AC
Specs: T
MDO1
IL
IH
TTL value.
, T
TTL value in DC Characteristics table
SDO1
In description column changed Phase to 0.
Description of Change
CY7C63310
CY7C638xx
CY7C639xx
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