DP83916VF National Semiconductor, DP83916VF Datasheet - Page 48

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

BUS INTERFACE PINS (Continued)
A31 –A1
RA5 –RA0
AS
ADS
MRW
MWR
INT
INT
RESET
S2 –S0
BSCK
BR
HOLD
BG
HLDA
BGACK
5 0 Bus Interface
Symbol
Driver
Type
TRI
TRI
TRI
TRI
TRI
TRI
OC
OC
TP
TP
TP
Direction
(Continued)
I O Z
I O Z
O Z
O Z
O Z
O Z
O Z
O Z
O
O
O
I
I
I
I
I
Address Bus These signals are used by the SONIC-16 to drive the DMA address after
the SONIC-16 has acquired the bus Since the SONIC-16 aligns data to word
boundaries only 23 address lines are needed
Register Address Bus These signals are used to access SONIC-16’s internal
registers When the SONIC-16 is accessed the CPU drives these lines to select the
desired SONIC-16 register
Address Strobe (AS) When BMODE
address The rising edge indicates the termination of the memory cycle
Address Strobe (ADS) When BMODE
address
When the SONIC-16 has acquired the bus this signal indicates the direction of data
Memory Read Write Strobe (MRW) When BMODE
read cycle and low during a write cycle
Memory Read Write Strobe (MWR) When BMODE
read cycle and high during a write cycle
Indicates that an interrupt (if enabled) is pending from one of the sources indicated by
the Interrupt Status register Interrupts that are disabled in the Interrupt Mask register
will not activate this signal
Interrupt (INT) This signal is active low when BMODE
Interrupt (INT) This signal is active high when BMODE
Reset This signal is used to hardware reset the SONIC-16 When asserted low the
SONIC-16 transitions into the reset state after 10 transmit clocks or 10 bus clocks if the
bus clock period is greater than the transmit clock period
Bus Status These three signals provide a continuous status of the current SONIC-16
bus operations See Section 5 4 3 for status definitions
Bus Clock This clock provides the timing for the SONIC-16 DMA engine
Bus Request (BR) When BMODE
attempts to gain access to the bus When inactive this signal is at TRI-STATE
Hold Request (HOLD) When BMODE
intends to use the bus and is driven low when inactive
Bus Grant (BG) When BMODE
pin low to indicate potential mastership of the bus
Hold Acknowledge (HLDA) When BMODE
SONIC-16 that it has attained the bus When the system asserts this pin high the
SONIC-16 has gained ownership of the bus
Bus Grant Acknowledge When BMODE
it has determined that it can gain ownership of the bus The SONIC-16 checks the
following signal before driving BGACK 1) BG has been received through the bus
arbitration process 2) AS is deasserted indicating that the CPU has finished using the
bus 3) DSACK0 and DSACK1 are deasserted indicating that the previous slave device
is off the bus 4) BGACK is deasserted indicating that the previous master is off the bus
This pin is only used when BMODE
TABLE 5-1 Pin Description (Continued)
48
e
1 this signal is a bus grant The system asserts this
e
e
Description
1 the SONIC-16 asserts this pin low when it
1
e
e
e
1 the falling edge indicates valid status and
0 the SONIC-16 drives this pin high when it
e
0 the rising edge indicates valid status and
e
1 the SONIC-16 asserts this pin low when
0 this signal is used to inform the
e
e
e
e
1 this signal is high during a
0 the signal is low during a
1
0