DP83916VF National Semiconductor, DP83916VF Datasheet - Page 56

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

5 0 Bus Interface
5 4 5 Master Mode Bus Cycles
In order to add additional compatibility with different bus
architectures there are two other modes that affect the op-
eration of the bus These modes are called the synchronous
and asynchronous modes and are programmed by setting
or resetting the SBUS bit in the Data Configuration Register
(DCR) The synchronous and asynchronous modes do not
have an effect on slave accesses to the SONIC-16 but they
do affect the master mode operation Within the particular
bus processor mode
modes are very similar This section discusses all four
modes of operation of the SONIC-16 (National Intel vs Mo-
torola synchronous vs asynchronous) when it is a bus mas-
ter
In this section the rising edge of T1 and T2 means the
beginning of these states and the falling edge of T1 and T2
means the middle of these states
5 4 5 1 Adding Wait States
To accommodate different memory speeds the SONIC-16
provides two methods for adding wait states for its bus op-
erations Both of these methods can be used singly or in
synchronous and asynchronous
(Continued)
56
conjunction with each other A memory cycle is extended by
adding additional T2 states The first method inserts wait-
states by withholding the assertion of DSACK0 1 STERM or
RDYi The other method allows software to program wait-
states Programming the WC0 WC1 bits in the Data Config-
uration Register allows 1 to 3 wait-states to be added on
each memory cycle These wait states are inserted between
the T1 and T2 bus states and are called T2(wait) bus states
The SONIC-16 will not look at the DSACK0 1 STERM or
RDYi lines until the programmed wait states have passed
Hence in order to complete a bus operation that includes
programmed wait states the DSACK0 1 STERM or RDYi
lines must be asserted at their proper times at the end of the
cycle during the last T2 not during a programmed wait
state The only exception to this is asynchronous mode
where DSACK0 1 or RDYi would be asserted during the last
programmed wait state T2 (wait) See the timing for these
signals in the timing diagrams for more specific information
Programmed wait states do not affect Slave Mode bus cy-
cles