DP83916VF National Semiconductor, DP83916VF Datasheet - Page 58

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DP83916VF

Manufacturer Part Number
DP83916VF
Description
IC CTRLR ORIENT NETWK IN 132PQFP
Manufacturer
National Semiconductor
Series
SONIC™r
Datasheet

Specifications of DP83916VF

Controller Type
Network Interface Controller (NIC)
Interface
Bus
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Voltage - Supply
-
Operating Temperature
-
Other names
*DP83916VF

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5 0 Bus Interface
5 4 5 3 Memory Cycle for BMODE
Asynchronous Mode
On the rising edge of T1 the SONIC-16 asserts ECS to
indicate that the memory cycle is starting The address
(A23 –A1) bus status (S2–S0) and the direction strobe
(MRW) are driven and do not change for the remainder of
the memory cycle On the falling edge of T1 the SONIC-16
deasserts ECS and asserts AS
In asynchronous mode DSACK0 1 are asynchronously
sampled on the falling edge of both T1 and T2 DSACK0 1
FIGURE 5-10 Memory Read BMODE
FIGURE 5-11 Memory Read BMODE
(Continued)
e
1
58
e
e
do not need to be synchronized to the bus clock because
the chip always resolves these signals to either a high or
low state If a synchronous termination of the bus cycle is
required however STERM may be used STERM is sam-
pled on the rising edge of T2 and must meet the setup and
hold times with respect to that edge for proper operation
Meeting the setup time for DSACK0 1 or STERM guaran-
tees that the SONIC-16 will terminate the memory cycle 1
1 Asynchronous (1 Wait-State)
1 Asynchronous (2 Wait-State)
TL F 11722 – 36
TL F 11722 – 37

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