CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 31

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

CY7C924ADX REFCLK Input Switching Characteristics
CY7C924ADX HOTLink Transmitter Switching Waveforms
Notes
Document #: 38-02008 Rev. *G
f
f
t
t
t
t
TXDATA[11:0]
20. When configured for synchronous operation with the FIFOs bypassed (FIFOBYP* is LOW), if RANGESEL is HIGH the SPDSEL input is ignored and operation
21. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
22. When transferring data to the Transmit FIFO from a depth expanded external FIFO (EXTFIFO = H), the data is captured from the external FIFO one clock cycle
Parameter
REF
REF
REFCLK
REFH
REFL
REFRX
Asynchronous (FIFO) Interface
Cascade Timing
Write Cycle
is forced to the 100–200 MBaud range.
within ±0.04% of the transmitter PLL reference (REFCLK) frequency.
following the actual enable.
TXEMPTY
TXSC/D*
TXHALF*
TXFULL
TXCLK
TXEN
REFCLK Clock Frequency—50 to 100 MBaud, 10-bit
mode, encoder bypass, REFCLK = 2x character rate
REFCLK Clock Frequency—50 to 100 MBaud,
8-bit mode, REFCLK = 2x character rate
REFCLK Clock Frequency—50 to 100 MBaud, 10-bit
mode, encoder bypass, REFCLK = 4x character rate
REFCLK Clock Frequency—50 to 100 MBaud,
8-bit mode, REFCLK = 4x character rate
REFCLK Clock Frequency—100 to 200 MBaud, 10-bit
mode, encoder bypass, REFCLK = character rate
REFCLK Clock Frequency—100 to 200 MBaud, 8-bit
mode, REFCLK = character rate
REFCLK Clock Frequency—100 to 200 MBaud, 10-bit
mode, encoder bypass, REFCLK = 2x character rate
REFCLK Clock Frequency—100 to 200 MBaud, 8-bit
mode, REFCLK = 2x character rate
REFCLK Period
REFCLK HIGH Time
REFCLK LOW Time
REFCLK Frequency Referenced to Received Clock Period
,
Description
t
TXCPWH
t
TXA
t
TXCLK
t
TXCPWL
t
TXENS
SPDSEL RANGESEL BYTE8/10*
[21]
0
0
0
0
1
1
1
1
t
Over the Operating Range
TXENH
Conditions
1
1
[20]
[20]
t
0
0
0
0
1
1
TXA
0
1
0
1
0
1
0
1
t
TXDS
16.67 33.33 MHz
16.67
–0.04 +0.04
Note 22
8.33
8.33
Min
6.5
6.5
10
20
10
20
25
CY7C924ADX
16.67 MHz
16.67 MHz
Max
33.3
120
20
40
20
40
Page 31 of 62
t
TXDH
MHz
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
%